Elantec Semiconductor, Inc.

Intersil Americas Inc.

National Semiconductor Corporation

Elantec, Inc.

Alexander Fairgrieve

Theodore D Rees

D Stuart Smith

Bill R Tang

Barry Harvey

Akihiro Asada

Xijian Lin

Yang Zhao

Miguel Gabino Perez

Systems, methods and devices provide for fast and power efficient transfer of three color data words (e.g., a M-bit red color word, a M bit green color word and a M-bit blue color word) per pixel from a controller to a laser diode driver (LDD). First and second transfer words are produced based on the three color data words. The first transfer word is transferred from the controller to the LDD and stored at LDD in response to a low-to-high portion of a cycle of a data transfer clock, and the second transfer word is transferred and stored in response to a high-to-low portion of a cycle of the data transfer clock. The first, second and third color data words are reproduced by the LDD in dependence on the first and second received transfer words. First, second and third DACs of the LDD are driven with the first color data word, the second color data word, and the third color data word. Three light sources (e.g., red, green and blue laser diodes or LEDs) are driven with output currents of the DACs.

Systems and methods for partitioned color, double rate video transfer

A transistor for use in an output stage is selectively part of one of two different circuits, one circuit being an electrostatic discharge (ESD) clamp circuit, the other circuit being an output stage circuit. For example, the transistor can be selectively connected such that it is part of the ESD clamp circuit, e.g., when a load (e.g., laser diode) connected to a current path terminal (e.g., drain or collector) of the transistor is not to be driven by a drive circuit. However, when the load connected to the current path terminal of the transistor is to be driven by the drive circuit, the transistor can be connected such that it receives a drive signal at its control terminal, from the drive circuit. This abstract is not intended to describe all embodiments of the present invention.

Self protecting output stage

Embodiments of the present invention relate to systems and methods for providing flexible multipulse strategies. In specific embodiments, a plurality of multipulse location registers are dedicated to storing multipulse location information. Each of a plurality of different mark-lengths that can result in at least one multipulse is mapped to one or more bit location within the multipulse location registers, such that a unique multipulse execution strategy can be defined for each of the plurality of different mark-lengths. Each bit location within the multipulse location registers can contain a first type of bit or a second type of bit. The first type of bit is used to indicate where to execute a multipulse, and the second type of bit is used to indicate where to not execute a multipulse. This abstract is not intended to be a complete description of the various embodiments of the present invention.

Flexible multipulse generator

Methods and system are provided for automatic power control of a laser diode, e.g., in a laser driver. In accordance with an embodiment of the present invention, a power controller includes a detector circuit adapted to detect the output of the laser diode and to produce a measured output therefrom. A comparator compares a desired output to the measured output, and produces an error signal therefrom. The error signal is provided to an integrator circuit that produces an integrated error signal. At least one digital-to-analog converter (DAC) uses the integrated error signal to produce a current drive signal that drives the laser diode.

Systems and methods for automatic power control of laser diodes

Optical pick-up units and laser drivers are disclosed, which can be used in various types of information recording/reproducing apparatuses, such as, but not limited to, DVD and CD drives, DVD camcorders, and DVD video recorders. A laser driver integrated circuit (LDIC) includes an automatic power controller, a running optical power controller, and a write strategy generator. The LDIC can be part of a chip-set, to be located on an optical pick-up unit (OPU). The chip-set can also include a power monitor integrated circuit (PMIC) to monitor the laser diode, and a photo-detector integrated circuit (PDIC) to detect light produced by the laser diode. The PMIC and the PDIC each include their own offset, gain and sample-and-hold circuitry.

Optical pick-up units and laser drivers with increased functionality

Methods and systems and apparatuses for reducing power consumption, in an environment including a laser driver that drives a laser diode, are provided. The voltage drop across a laser diode, driven by a laser driver, is monitored. This enables a supply voltage, used to power the laser driver, to be appropriately adjusted, based at least in part on the monitored voltage drop. For example, the supply voltage is increased when the monitored voltage drop across the laser diode increases, and decreased when the monitored voltage drop across the laser diode decreases.

Adjustable power control for laser drivers and laser diodes

A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors and with an NMOS transistor providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors and provide loads for the differential transistor and . Transistors and together with an amplifier provide biasing for the delay device. The amplifier has a non-inverting input set to V &minus;V . As configured, a constant output voltage swing from V to V &minus;V is provided at the outputs V &plus; and V &minus; of the delay device, independent of a control voltage V used to set the tail current. The NMOS load transistor , as opposed to the PMOS transistor in FIG. , does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current. A wide frequency tuning range of a ring oscillator using the delay circuit of FIG. is provided because the operating frequency for a ring oscillator will be directly proportional to the tail current through transistor

High speed, low-power CMOS circuit with constant output swing and variable time delay for a voltage controlled oscillator

The present invention is a differential amplifier with circuitry to eliminate the effect of transistor impedance other than an actual load impedance on voltage gain. The circuitry includes a pair of transistors 400 and 402, each with a base connected to a respective input of the differential amplifier along with a similar base connection of a respective one of transistors 100 and 102, and an emitter connected to a current source 404. A collector of transistor 400 is connected through transistor 410 to the emitter of a current sink transistor 306, while the collector of transistor 402 is connected through transistor 412 to the emitter of a current sink transistor 308. Operational amplifiers (opamps) 420 and 422 serve as voltage followers to connect the collector of transistor 100 to the base of transistor 412, and the collector of transistor 102 to the base of transistor 410. An inverting input of the opamps 420 and 422 are connected to the emitter of transistors 410 and 412 to eliminate the effect of a emitter to base voltage drop in transistors 410 and 412. With such components, loading at the outputs V.sub.OUT and V.sub.OUTB is substantially limited to the actual load provided by transistors 306 and 308 and resistors 316 and 318.

Differential amplifier with improved voltage gain using operational

A circuit for generating an output signal used for driving a grounded load is provided. The circuit provides an output signal without glitches or spikes. The circuit also outputs a drive signal with enhanced responsiveness in transitioning from one output value level to another output value level. The circuit includes a plurality of control devices for providing respective output signals responsive to respective control signals. The base of a PNP transistor is coupled to the output of the control devices and acts as a buffer. The emitter of the PNP transistor is coupled to a voltage source and the collector is coupled to a grounded load for providing the drive current. Alternatively, an NPN transistor and current source provides the drive current to the grounded load. The circuitry may be used in an optical disk drive with the load and ground being a laser diode used for providing a laser beam in reading/writing an optical disk.

Reduced output capacitance circuit for driving a grounded load in

A variable frequency oscillator providing a constant amplitude with variations in frequency. The variable frequency oscillator includes: an oscillator having an input connected for receiving a current I.sub.1, and outputs for providing complementary signals having a frequency varying in proportion to the current I.sub.1 ; first and second transistors, each having a base connected to a respective one of the oscillator outputs; current supply circuitry having a first output connected to the input of the oscillator for providing the current I.sub.1, and a second output connected to the emitters of the first and second transistors for providing a current I.sub.3, the current I.sub.3 varying in proportion to the current I.sub.1, without varying significantly due to changes in the oscillator frequency; and first and second output amplifiers, each having an input connected to the collector of a respective one of the first and second transistors, and an output for providing a signal which varies in proportion to the current I.sub.3 and varies inversely proportion to the oscillator frequency. With such circuitry, variations in amplitude of signals driving the output amplifiers due to changes in oscillator frequency will cancel inverse variations in amplitude of signals at the outputs of the output amplifiers due to the changes in the oscillator frequency.

Constant amplitude vs. frequency oscillator

A circuit used with a differential amplifier to eliminate the effect of Early Voltage from voltage gain provided by the differential amplifier. With a differential amplifier utilizing PNP transistors which experience the lowest, and most undesirable Early Voltage, the circuitry includes a pair of transistors 400 and 402, each with a base connected to an input of the differential amplifier corresponding to a similar base connection of a respective one of transistors 100 and 102 of the differential amplifier, an emitter connected to a current source, and a collector connected to the collector of a respective one of NPN current sink transistors 306 and 308 connected at outputs of the differential amplifier. The circuitry for elimination of Early Voltage further includes components to assure the collector voltages of transistors 400 and 402 are equal and the collector voltages of transistors 102 and 400 are equal. In addition to circuitry for elimination of Early Voltage when PNP transistors 100 and 102 are used to provide the differential amplifier inputs, the circuitry may also be configured for use when NPN transistors provide inputs for a differential amplifier.

Differential amplifier with improved voltage gain

The input capacitance of a differential amplifier is reduced by connecting a positive feedback path between the collector of each input transistor and a terminal of a resistor connected in the other parallel current path. The positive feedback paths cause the voltage at the collector of each input transistor to move in the same direction as the voltage at the base of that input transistor, and thereby reduce the effective input capacitance seen at the input terminals of the differential amplifier.

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Menlo Park, CA, United States of America

Alexander Fairgrieve