Arm Limited

Asymptote Limited

Alexander Edward Nancekievill

Rupert Rutledge

David James Seal

A remote system for monitoring and controlling one or more devices for use in the cryogenic processing of a sample is provided. A remote server capable of transmitting freezing profile data to one or more freezers, transmitting transportation profile data to one or more transportation devices, and transmitting thawing profile data to one or more thawing devices. The remote server is also capable of receiving detected data from the one or more freezers relating to the freezing of a sample in accordance with the freezing profile data, receiving detected data from the one or more transportation devices relating to the transportation of a sample in accordance with the transportation profile data, and receiving detected data from the one or more thawing machines relating to the thawing of a sample in accordance with the thawing profile data.

Systems and methods for remotely monitoring the cryogenic processing of samples

A data processing systemincorporating an instruction pipelineand a prefetch unitis provided with a branch prediction mechanism using both a branch prediction memorystoring 1-bit values indicating strongly taken or strongly not taken together with a branch prediction cache indicating for certain selected branch history values either weakly taken or weakly not taken predictions. When a conditional branch instruction is encountered, then the preceding branch prediction history is used to access a first prediction within the branch prediction memoryand is looked up to check for a hit within the branch prediction cache. If a hit occurs, then a second prediction within the branch prediction cacheis used in preference to the first prediction, otherwise the first prediction is used. The misprediction by a first prediction value stored within the branch prediction memorytriggers a second prediction to be cached within the branch prediction cachecorresponding to that mispredicted history value.

Branch prediction mechanism including a branch prediction memory and a branch prediction cache

A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they recur their termination can be predicted. This enables program loops which are longer in length than can be represented within a reasonably sized branch prediction memory to nevertheless be detected and have their loop ends predicted.

Branch prediction mechanism using a branch cache memory and an extended pattern cache

A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value not being masked in order to generate a masked rotated data value; a selected bit of said rotated data value are masked with other bits of said rotated data value not being masked in order to generate a bit preset rotated data value; and said sign-extended bit field extracted data value to be generated by subtracting said masked rotated data value from said bit preset data value or said zero-extended bit field extracted data value to be generated by performing a logical exclusive-OR operation with the masked rotated data value and said bit preset data value.

Bit field extraction with sign or zero extend

The present invention provides an apparatus and method for processing data using a multiplying circuit for performing a multiplication of a W/2 bit data value by a W bit data value. An instruction decoder is provided which is responsive to a multiply instruction to control the multiplying circuit to generate a multiplication result for the computation M&times;N, where M and N are W bit data words. The multiplying circuit is arranged to execute a first operation in the which the data word N is multiplied by the most significant W/2 bits of the data word M to generate a first intermediate result having 3W/2 bits, and to then execute a second operation in which the data word N is multiplied by the least significant W/2 bits of the data word M to generate a second intermediate result having 3W/2 bits. The first intermediate result is shifted by W/2 with respect to the second intermediate result and added to the second intermediate result to generate the multiplication result. By performing the two parts of the multiplication in reverse order to the conventional approach, it has been found that the complexity of the circuitry can be reduced, and a reduction in power consumption can be achieved.

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Cambridge, United Kingdom

Alexander Edward Nancekievill