Stmicroelectronics Gmbh

Alexander Driker

Sivagnanam Parthasarathy

Cristian Duroiu

A method for computing the alignment sticky bit in floating-point operations is provided. The method includes computing a pre-computed sticky bit. A significand is aligned based on an alignment counter. A shifter sticky OR is computed. The alignment sticky bit is computed based on the pre-computed sticky bit by ORing the pre-computed sticky bit and the shifter sticky OR when the alignment counter comprises a value greater than or equal to a predefined value.

Method and system for computing alignment sticky bit in floating-point operations

A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the exponent of the result may be adjusted due to normalization or renormalization. The exponent adjustment due to renormalization or the exponent adjustment due to normalization and renormalization is combined with the significand rounding operation.

Apparatus and method for adjusting exponents of floating point numbers

A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction transaction employed to provide operands and instructions to an extension unit and retrieve results from the extension unit. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow new computational instructions to be introduced without regeneration of the processor architecture. Support for multiple extension units and/or multiple execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within extension units, extension unit instruction predicates, and for handling processor core stalls and result save/restore on interrupt is included.

Coprocessor extension architecture built using a novel split-instruction transaction model

An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID.

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Alexander Driker