International Standard Electric Corporation

Alexander Douglas Odell

Kenneth A Arton

John M Young

This relates to an MOS logic synchronizing circuit operating with a single phase clock waveform. A logic inverter has two parallel-connected switching MOST's, the gate of one (M4) being connected to clock and the gate of the other (M2) being coupled to the logic input via the source-drain path of a third MOST (M1) whose gate is connected to clock. Input signal change is delayed by a full clock period.

Logic transfer circuit employing MOS transistors

This invention relates to a Schmitt trigger circuit, and particularly to a Schmitt trigger circuit comprising MOS transistors. The all MOS transistor Schmitt trigger circuit has a first MOS input inverting amplifier regeneratively coupled with a further MOS transistor to provide the requisite positive feedback voltage, and a second MOS input inverting amplifier, not in the feedback loop but having the feedback voltage also applied thereto, the output being taken from the second inverter. Separation of output from the feedback loop gives flexible control of input triggering points and output characteristics. This circuit is intended for use in a MOS IC telephone switching cross-point switch.

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Great Dunmow, United Kingdom

Alexander Douglas Odell