Sun Microsystems, Inc.

Rockwell International Corporation

Agate Logic, Inc.

Alexander Dougald Taylor

Michael A Ang

Jonathan E Starr

Sai V Vishwanthaiah

Colin Neal Murphy

Craig E Borden

Jason Golbus

Miguel A Martinez

A system for general purpose input-output (IO), including a first pad; an IO buffer comprising the first pad; and an IO datapath logic block operatively connected to the IO buffer, where the IO datapath logic block and the IO buffer are associated with a general purpose IO block in a heterogeneous configurable integrated circuit (HCIC).

General purpose input/output system and method

A driver capable of launching signals into a transmission line and of terminating signals at a receiver end of the transmission line includes within the driver a circuit for controlling the output impedance and a circuit for controlling the output slew rate. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes. The pull up circuit includes pull up output circuit and an impedance control buffer circuit, a parallel pull up circuit, the parallel pull up circuit and the pull up output circuit being controllable to adjust the impedance of the pull up circuit. The driver also includes a pull down circuit coupled to receive at least one of the plurality of control codes. The pull down circuit includes at least one pull down output circuit and a parallel pull down circuit, the parallel pull down circuit being controllable to adjust the impedance of the pull down circuit. The output impedance of the driver is further controlled during transitional phases of turning on and turning off the pull down circuit and the pull up circuit under a plurality of process, voltage and temperature (PVT) conditions.

Dynamic termination logic driver with improved impedance control

An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines. The structures and methods are useful on a power supply board to attenuate periodic ripple voltages produced by a DC-DC converter. In general, the structures and methods are applicable in any application with a period ripple voltage.

Voltage regulator circuit for attenuating inductance-induced on chip supply variations

Differencing non-overlapped dual-output amplifier circuit

A method may be provided which controls the output impedance of a driver which includes within the driver an impedance circuit and a slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a method also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Method for an output driver with improved impedance control

A driver may be provided which controls output impedance of a driver which includes within the driver an impedance circuit and slew rate control. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Output driver with improved impedance control

A method of controlling impedance of a driver capable of launching signals at a driving end of a transmission line and capable of terminating signals at the receiver end of the transmission line controls the impedance of the driver across process, voltage, and temperature (PVT) variations by selectively enabling and disabling at least one of a plurality of output elements according to an impedance control code. The impedance control code compensates for variations in output impedance due to PVT variations. The method includes selectively enabling and disabling the plurality of output elements so that a direct current impedance of a parallel combination of the plurality of output elements is within a predetermined percentage of the impedance of the transmission line, and sizing the plurality of output elements to account for a predetermined range of PVT conditions, and selectively enabling and disabling the plurality of output elements to allow an impedance of the driver to be approximately equal to the impedance of the transmission line when an output voltage from the driver is approximately half the first supply voltage. The sizing of a plurality of transistors within the plurality of output elements is such that the direct current impedance of a parallel combination of the plurality of output elements is approximately equal to the impedance of the transmission line when the output voltage is half the supply voltage.

Method for a dynamic termination logic driver with improved impedance control

A dynamic termination logic driver, one that is capable of launching signals at a driving end of a transmission line and is capable of terminating signals at a receiver end of the transmission line, controls output impedance and includes within the driver an impedance circuit and slew rate control. Accordingly, a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit coupled to receive at least one of a plurality of control codes and the driver also includes a pull down circuit coupled to receive at least one of the plurality of control codes. The output impedance of the driver is further controlled during transitional phases of tuning on and turning off the pull down circuit and the pull up circuit under a plurality of process, voltage and temperature (PVT) conditions.

Method for a dynamic termination logic driver with improved slew rate control

A dynamic termination logic driver, the driver capable of launching signals at a driving end of a transmission line and terminating signals at a receiver end of the transmission line, controls slew rate over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit having an impedance, the pull up circuit including a pull up output circuit and a buffer circuit, the pull up output circuit including a parallel pull up circuit, a pull up output control circuit, and a pull up slew rate control circuit, wherein the parallel pull up circuit and the pull up output control circuit are coupled in parallel. The driver also includes a pull down circuit having an impedance, the pull down circuit including at least one pull down output circuit, the at least one pull down output circuit including at least one pull down slew rate control circuit, a parallel pull down circuit and a pull down output control circuit, wherein the parallel pull down circuit and the pull down output control circuit are coupled in parallel. The driver also includes a plurality of output elements within the pull up circuit and the pull down circuit, wherein the plurality of output elements are selectively enabled and disabled with a controlled slew rate. The selective enabling and disabling is based on an impedance control code.

Dynamic termination logic driver with improved slew rate control

A driver may be provided which controls the output slew rate a driver which includes within the driver a slew rate control circuit. Accordingly, a desired output slew rate can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Output driver with improved slew rate control

A method for a driver may be provided which controls the output slew rate of a driver which includes within the driver an impedance control and a slew rate circuit. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a method also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Method for an output driver with improved slew rate control

An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Differential receiver

A method for determining bit element values for an impedance control circuit is provided which controls the output impedance of drivers which are coupled to the impedance control circuit. Accordingly, a desired driver output impedance can advantageously be established and maintained over a wide range of variations in operating conditions and manufacturing processes. Thereby shortening the signal settling time and increasing the attainable signaling frequency.

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Cupertino, CA, United States of America

Alexander Dougald Taylor