Cisco Technology, Inc.

International Business Machines Corporation

Ip-first, LLC

Alexander Dankwart Essbaum

Aubrey Deene Ogden

Mark J Brazell

Brian Allan Zoric

A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the block is determined along with the netlist. The sum of the areas of the functional cells and the desired spare cell area is used as the area of the block boundary. The boundary is provided as input to an auto-placement tool along with the netlist and the list of functional cells. The list of functional cells specifically does not include the spare cells so that the tool does not place spare cells in the boundary. Consequently, the spare cell area may be utilized as wiggle-room by the tool to efficiently place the functional cells. The tool produces a placement of the functional cells that includes white space in the boundary. Spare cells are then placed into the white space.

Method for allocating spare cells in auto-place-route blocks

A router coupled to a plurality of networks receives a data packet from a first one of the networks and routes the data packet to a second one of the networks. The data packet includes a first portion having a destination network address. The router receives a first portion of the data packet, and the first portion of the data packet includes a destination network address. The destination network address of the data packet is asserted to a content addressable memory (&ldquo;CAM&rdquo;), where the CAM has stored routing information, while the first packet is not yet fully received from the first network. The CAM identifies one of the networks coupled to the router, in response to the destination network address being in the CAM, while the router is still receiving a remaining portion of the data packet. After identification of the destination network the data packet is routed to the destination network. However, in response to the destination network address not being in the CAM, the data packet is received completely, and a database searched for the destination network address, and the data packet is forwarded after the destination address is found in the database. The destination address may then be written into the CAM.

Method and apparatus for message routing, including a content addressable memory

In a router coupled to a number of networks, a data packet is received from a first one of the networks and routed to a second one of the networks. The data packet includes a first portion having a destination network address. The destination network address for the data packet is input to a content addressable memory (&ldquo;CAM&rdquo;) while the router is still receiving at least a portion of the data packet, so that the CAM, having network address information stored therein, identifies one of the networks coupled to the router and corresponding to the destination address of the data packet while the router is still receiving at least a portion of the data packet.

A cell apparatus and method for use in building complex integrated circuit devices. The cell apparatus and method for use in building complex integrated circuits includes a cell which has regions dedicated to specific types of circuit elements and a method for designing the cell. A first region within the cell is dedicated to a first type of circuit element. A second region within the cell is dedicated to a second type of circuit element. A third region is dedicated to one or more diverse types of integrated circuit elements for utilization in multiple diverse applications of integrated circuits. The cell can be utilized in conjunction with multiple cells to efficiently form an image representing a complex integrated circuit device. The cell includes an upper edge and a lower edge, a plane dedicated to a ground line, a plane dedicated to a clock line, and a plane dedicated to a voltage supply line. The first region within the cell can specifically be dedicated to n-type transistors and the second region to p-type transistors. A central region located within the cell divides the first region and the third region from the second region. The cell can be duplicated multiple times to build a library of dynamic logic cells such as those used in integrated circuit macros.

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Austin, TX, United States of America

Alexander Dankwart Essbaum