Thinking Machines Corporation

Alexander D Vasilevsky

Tobias M Weinberg

Lisa A Tennies

Gary W Sabot

David C Douglas

Brewster A Kahle

Clifford A Lasser

Kenneth W Crouch

Linda J Seamonson

Shaw W Yang

David P Christman

David F Lively

A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.

Compiling a source code vector instruction by generating a subgrid loop

A system and method for optimizing statements to produce more efficient assembly language for use in a parallel processing environment. In doing this, the present invention separates elemental from non-elemental nodes in a statement, encapsulates the elemental statements, and generates a parallel assembly language code stream from encapsulated statements, and a scalar code stream from scalar statements and non-elemental nodes (for which the scalar assembly language is used to utilize a non-elemental resolver).

System and method for optimizing and generating computer-based code in a

The present invention provides a parallel vector machine model for building a compiler that exploits three different levels of parallelism found in a variety of parallel processing machines, and in particular, the Connection Machine.RTM. Computer CM-2 system. The fundamental idea behind the parallel vector machine model is to have a target machine that has a collection of thousands of vector processors each with its own interface to memory. Thus allowing a fine-grained array-based source program to be mapped onto a course-grained hardware made up of the vector processors. In the parallel vector machine model used by CM Fortran 1.0, the FPUs, their registers, and the memory hiearchy are directly exposed to the compiler. Thus, the CM-2 target machine is not 64K simple bit-serial processors. Rather, the target is a machine containing 2K PEs (processing elements), where each PE is both superpipelined and superscalar. The compiler uses data distribution to spread the problem out among the 2K processors. A new compiler phase is used to separate the code that runs on the two types of processors in the CM-2; the parallel PEs, which execute a new RISC-like instruction set called PEAC, and the scalar front end processor, which executes SPARC or VAX assembler code. The pipelines in PEs are filled by using vector processing techniques along the PEAC instruction set. A scheduler overlaps the execution of a number of RISC operations.

System and method for compiling a fine-grained array based source

A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors. In accordance with a preferred embodiment of the invention, three or more transposers are used in connection with each word-oriented processor so as to provide a pipelining capability that significantly enhances processing speeds.

Method and apparatus for interfacing bit-serial parallel processors to a

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Watertown, MA, United States of America

Alexander D Vasilevsky