Network Appliance, Inc.

Silicon Graphics, Incorporated

Alexander D Petruncola

Jeffrey S Kimmel

Robert M English

Kayuri Hasmukh Patel

Raymond C Chen

Naveen Bali

Grace Ho

Nawaf K Bitar

Rajagopal Ananthanarayanan

Nareshkumar Maganlal Patel

David Craig

In a processing system which includes a physical processor that includes multiple logical processors, multiple domains are defined for multiple processes that can execute on the physical processor. Each of the processes is assigned to one of the domains. Processor utilization associated with the logical processors is measured, and each of the domains is allocated to a subset of the logical processors according to the processor utilization.

Method and apparatus for allocating shared resources to process domains according to current processor utilization in a shared resource processor

A storage server provides a set of client devices with access to a set of mass storage devices. The storage server receives requests from the client devices, each request representing a storage operation to be performed by the storage server on the set of mass storage devices. The storage server maintains a log of write requests received from the client devices, the log including a separate log entry for each of the write requests, and a separate checksum in each of the log entries. Each checksum is for use by a checksum algorithm in determining data integrity of the corresponding log entry. The checksum algorithm is selected, from among a number of selectable a checksum algorithms, based on one or more predetermined criteria, such as a desired balance between performance and checksum strength.

Verification of file system log data using per-entry checksums

A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location. The program counter value is then written to the first register and a jump performed to the program counter value stored in the first register while the last remaining register value is loaded to the first register. Each of these steps is performed in user mode; the result is an efficient way of switching from one user thread to the next user thread without entry into kernel space.

Resumption of preempted non-privileged threads with no kernel

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San Jose, CA, United States of America

Alexander D Petruncola