Silicon Laboratories Inc.

Alexander Cherkassky

Bruce Philip Del Signore

An interpolative divider divides an input clock signal according to a divide ratio and supplies an output clock signal. An integer divider receives the input clock signal and supplies an integer divider output signal. A phase interpolator is coupled to the integer divider and delays the integer divider output signal according to a quantization error. The phase interpolator includes first and second current sources. The first current source turns on k unit current elements during a first part of a charging cycle to charge a first capacitor to a first voltage, 0≤k≤M, k and M are integers, and k is determined by the digital quantization error. The second current source turns on k+M unit elements to charge a second capacitor during a second part of the charging cycle. The output clock signal transitions when the first voltage equals the second voltage.

Interpolative divider

A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

High output swing high voltage tolerant bus driver

Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90&#xb0; apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Synchronous detection circuit and method for determining a bio-impedance of a biological tissue

Synchronous detection circuit and method for extracting magnitude and phase from a waveform

A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period &#x394;T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period &#x394;T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

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Hollis, NH, United States of America

Alexander Cherkassky