Advanced Micro Devices Corporation

Seagate Technology Incorporated

Alexander C Tain

James J Casto

Valerie Vivares

Charles Anderson

Mohammad A Khan

Shrikar Bhagath

Jonathan D Halderman

Tom Ley

Quang Nguyen

Pranabendra Sarma

Emmanuel Atta

Kris Shih-Yen Chou

Ratnakar Dadi

Subodh Yashwant Bhike

Joan L Tan

Karthik Chandrasekar

Shawn Tzung-Sheng Lo

Georg Kuhnke

A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.

Package grounding system

An arrangement and method of reconfiguring a circuit board and package arrangement employs one-time programmable elements on a package to allow a programmable first package arrangement having a first package board and a first integrated circuit to be readily replaced. The first package arrangement was programmed to operate with a first set of operating parameters. The replacement package arrangement, having a second package board and a second integrated circuit, may be substantially identical to the first package arrangement except programmed to operate with a second set of operating parameters different from the first set of op crating parameters. The replacement of the first package arrangement by the second, differently programmed package arrangement, provides a reconfigured circuit board and package arrangement while avoiding the obsoleting of the circuit board.

Method and apparatus for reconfiguring circuit board and integrated circuit packet arrangement with one-time programmable elements

A digital computer automatically converts an input representation of a pattern of flip-chip integrated circuit interconnect bumps in a format suitable for a circuit design program into an output representation in a format suitable for a package design program. A converter program is adapted by script files to convert the input representation into an intermediate representation in a format suitable for a mechanical design program in which only a layer which includes the bumps is extracted from the input representation which can include a substantial number of layers. A mechanical design program is adapted by scripts to automatically input the intermediate representation, identify and label the interconnects, and create the output representation in which the interconnects are labeled. The mechanical design program can be further adapted by scripts to rotate, mirror and/or shrink the pattern. A package design program inputs the output representation and draws the labeled interconnects. A comparator program compares the output representation with a previously created output representation to identify differences therebetween.

Computer implemented method and program for automating flip-chip bump layout in integrated circuit package design

A novel method is provided for checking BGA substrate design made using an APD design tool. User's netlist containing information on a die to be mounted on the BGA substrate is entered into an interface software system providing an interface to the APD design tool. The interface software system extracts the design netlist generated from the APD design of the BGA substrate, and compares this netlist to the user's netlist. If no differences are reported, the BGA substrate design is considered to be correct.

Method of checking BGA substrate design

An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first end and a second end separated by a programmable link. The programmable element is positioned on a surface other than the top surface, e.g., a side surface or the bottom surface of the package substrate to render them less conspicuous to unscrupulous suppliers intent on tampering with the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Integrated circuit package incorporating camouflaged programmable elements

An integrated circuit arrangement comprising an integrated circuit package having a package board. An integrated circuit die is mounted to a surface of the package board. A spring frame is mounted to the package board surface at a pair of opposite frame bends. The spring frame has a central opening that receives the integrated circuit die. Sides of the spring frame away from the bends are raised from the package surface. A heat sink is mounted to the spring frame such that a bottom of the heat sink contacts an upper surface of the integrated circuit die as the heat sink pushes the sides of the spring frame toward the package surface.

Spring frame for protecting packaged electronic devices

A novel method of automatically routing connections from bumps on a die to package pins in an advanced IC package such as a flip-chip package. The method involves creating graphic presentations of the die having the bumps and the package having pins, and placing the graphic presentation of the die into the graphic presentation of the package. If a netlist identifying interconnections between the bumps and the pins is available, the best route from a bump on the die to a corresponding package pin identified in the netlist is generated in accordance with preset requirements. If the netlist is not available, the best route from the bump to any package pin is generated in accordance with the preset requirements.

Single-layer autorouter

A flip chip package compatible with first and second die footprints includes an interconnection substrate having a connection surface configured to receive an integrated circuit die that has either a first or a second die footprint. The interconnection substrate has a plurality of conductive pads on its connection surface for establishing a connection to the conductive pads of the selected integrated circuit die. The connection surface conductive pads have a first section corresponding to the conductive pads of an integrated circuit with a first die footprint. It also has a second section corresponding to the conductive pads of an integrated circuit with a second die footprint. The first and second sections of conductive pads overlap, reducing the size of the package footprint while allowing the same package to be used with different integrated circuit dies.

Flip chip package compatible with multiple die footprints and method of assembling the same

A method and apparatus for automatically verifying the design of an IC package is provided. First, data specifying the location of solder balls on the IC device is compared to data specifying the physical location of corresponding pads on the package to determine whether the IC die physically matches the package. Then, data specifying electrical signals associated with the IC die is compared to data specifying electrical signals associated with the package to determine whether the IC die logically matches the package. Finally, data specifying electrical signals associated with pins on the package is compared to data specifying electrical signals associated with a socket to determine whether the package logically matches the socket. If the IC die physically and logically matches the package and if the package logically matches the socket, then the design of the IC package is verified.

Integrated circuit package verification

A system and method which includes a user interface for automation of the build sheet is provided. The database icon or command of the user interface is executed to select an appropriate package for an IC chip, and a blank bond master is downloaded to the hard disk of the work station. The engineer can choose either the suggest die icon/command or the die cleaner icon/command to create an image file of the die pad ring based on a mask layer best representative of the die pad ring. Thereafter, the die pads and bond fingers are identified and a net list is complied when the wire bonding icon or command is executed to create a bonding device diagram without the die image. A die image is created based on a mask layer best representative of the die using either the TIF to AutoCAD icon/command or the GDS to AutoCAD icon/command. The Die Image Merge icon/command merges the die image with the bonding device diagram to complete the build sheet. Thereafter, an IC package may be fabricated based on the bonding device diagram.

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Milipitas, CA, United States of America

Alexander C Tain