National Semiconductor Corporation

Vivid Engineering, Inc.

Alexander Burinskiy

Vladislav Potanin

Elena Potanina

Peter J Hopper

Vladislav Vashchenko

William James McIntyre

Luan Minh Vu

Frank John De Stasi

Nathanael Griesert

Vladimir Kuznetsov

John Philip Parry

James Steven Brown

Arun Rao

Technologies are generally described for an integrated circuit that is designed to serve as the basis of SONAR sensors that provide high sensitivity, low noise, low cost, and electronically adjustable gain in a small package may incorporate transducer drivers and signal sensing functions. Electronically programmable gain of the circuit may provide flexibility in system designs for gain management, and eliminate a need for manual gain adjustments in production. Power may be supplied to the sensor(s) over a power line of the circuit from a direct current source through a resistor. The same line may also be used for communicating with the sensor(s). Data from the microcontroller may be transmitted to the sensor(s) using an open-drain driver transistor and received through another transistor isolating the micro-controller's input from potentially high voltages present on the power line.

Ultrasonic distance measurement controller

A power-on reset (POR) circuit is provided. The POR circuit includes a first current source, a second current source, and a current comparator. The first current source is arranged to provide a relatively supply-independent circuit. The second current source is arranged to provide a supply-dependent current. The current comparator is arranged to compare the relatively supply-independent circuit with the relatively supply-dependent current to provide a POR signal.

Apparatus and method for power-on reset circuit with current comparison

A method for providing feed forward compensation in a drive signal for a rapid resonant frequency change due to a rapid LASER intensity change upon a micro-electro-mechanical system (MEMS) mirror and/or a surrounding MEMS structure in a MEMS scanner causing a mirror temperature change is provided. The method includes determining an intensity factor for at least one laser beam projected onto the MEMS scanner and adjusting a drive frequency of the drive signal based on the intensity factor. The intensity could represent a single intensity factor for multiple laser beams projected onto the MEMS scanner. The method could also include delaying the adjustment of the drive frequency to allow the resonant frequency change to take affect in the MEMS scanner. Delaying the adjustment could include delaying delivery of the intensity factor such that the intensity factor is provided coincident with the resonant frequency change of the MEMS scanner.

Method and system for providing resonant frequency change compensation in a drive signal for a MEMS scanner

In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.

ESD protection device with controllable triggering characteristics using driver circuit related to power supply

A buck DC to DC converter is arranged to more accurately regulate an output voltage by substantially eliminating a ground voltage error caused at least in part by parasitic resistance during low side conversion/regulation. During high side conduction of the high side switch, the converter employs the output voltage for error correction. And during low side conduction of the low side switch, the converter employs a sampled and held version of the output voltage for error correction which enables the converter to eliminate the ground voltage error caused by parasitic resistance.

Ground voltage drop reduction circuit for a buck DC-DC converter

A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.

Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter

The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.

Level shifter that provides high-speed operation between power domains that have a large voltage difference

A circuit for regulating a sensed current in a power transistor is provided. The circuit is configured to sense if the drain current of the power transistor has reached a limit current I. A sense transistor is arranged in an m:1 current mirror relationship with the power transistor. Additionally, a current sink that is coupled to the drain of the sense current is also configured to sink a current approximately equal to I/m. Further, a comparison circuit is configured to compare the drain voltages of the power and sense transistors. Also, if the drain current of the power transistor is less than I, a current sink pulls down the drain of the sense transistor, so that the drain voltage of the sense transistor is less than the drain voltage of the power transistor. However, if the level of the drain current of the power transistor reaches I, then Vds of the sense transistor would reach Vds of the power transistor, and the comparator would trip. Additionally, two switches are arranged to be open when switching currents flowing through the power transistor and sense transistors are each substantially zero. By opening the switches when these switching currents are each substantially zero, a false output (trip) of the comparison circuit can be prevented.

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San Jose, CA, United States of America

Alexander Burinskiy