Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Alexander Bazarsky

Eran Sharon

Ariel Navon

Ran Zamir

Yehuda Hahn

Shay Benisty

Idan Alrod

David Avraham

Omer Fainzilber

Stella Achtenberg

Tomer Tzvi Eliash

Idan Goldenberg

Karin Inbar

Rami Rom

Michael Micha Ionin

Dudy David Avraham

Alon Marcu

Daniel Joseph Linnen

Ofir Pele

Yuval Grossman

Ishai Ilani

Yoav Markus

Michael Ionin

William Bernard Boyle

Avichay Haim Hodes

Evgeny Mekhanik

Opher Lieber

Nika Yanuka

David Gur

Sergey Anatolievich Gorobets

Nian Niles Yang

Grishma Shah

Jack Frayer

Tien-Chien Kuo

Tz-Yi Liu

Gadi Vishne

Philip David Reusswig

Tomer Eliash

David Rozman

Alon Eyal

Ofer Shapira

Joshua Lehmann

Roi Kirshenbaum

Alexander Kalmanovich

Micha Yonin

Itay Busnach

Yan Li

Yu-Chung Lien

Tianhong Yan

Amit Kumar Sharma

Julian Vlaiko

Rohit Sehgal

Abhinandan Venugopal

Xinmiao Zhang

Vinayak Bhat

Eyal Sobol

Noam Presman

Yan Dumchin

Yuri Ryabinin

Danny Berler

Mahim Raj Gupta

A Harihara Sravan

Arthur Shulkin

Noga Deshe

Lola Grin

Aki Bleyer

Lior Avital

Lior Bublil

Yuval Bahar

Gilad Koren

Tsiko Shohat Rozenfeld

Jonathan Sokolowski

Martin Booth

Sanel Alterman

Ofer Privman

Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.

Detection of data storage device removal

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Non-volatile memory die with deep learning neural network

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.

Read-protected storage device with sequential logging

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Adaptive use of multiple channels in a storage device

A DNA-based storage system includes an error correction system operable to: (a) identify a DNA codeword from a DNA sequencing operation; (b) calculate an initial syndrome weight; (c) determine that the initial syndrome weight is greater than a predetermined threshold; (d) perform an alignment alteration in the information segment by: (i) selecting a skew point within the information segment; (ii) performing an indel operation on the information segment at the skew point; (iii) calculating a modified syndrome weight; (iv) comparing the initial syndrome weight with the modified syndrome weight; and (v) incorporating the indel operation into the information segment when the comparing indicates an improvement in the modified syndrome weight; (e) decode the modified codeword; and (f) transmit the contents of the output file to a computing device, the output file representing user data stored within the DNA molecule.

Error correction systems and methods for DNA storage

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Memory (NVM) devices for use with recurrent neural networks

Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Optimized power up in storage memory devices

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Write coalescing via HMB to optimize write performance

Storage devices are configured to be utilized in a variety of blockchain related activities that rely on a proof of space consensus model. These storage devices are required to process a lot of read and write cycles on their memory devices to generate the desired proof of space consensus data. The generation and storing of this generated data requires very different types of memory device usage. Storage devices may be configured with a first partition for high-speed access for generating the data, while a second partition is also configured for long-term storage of the generated data. As memory devices reach their estimated end-of-life, they can be dynamically reassigned to the second partition. Likewise, some storage devices may be equipped with multiple memory arrays of different types of memory devices. One set of memory devices can be used for generation, while cheaper, write-once or few memory devices are provided for storage.

Cold storage partition management in proof of space blockchain systems

A DNA-based storage system implements a sub-code architecture for error correction capability (ECC) purposes. The sub-code architecture enables a long DNA strand to be divided into two or more short DNA strands. Each short DNA strand has its own unique parity information. Additionally, each short DNA strand is separately decodable from the other short DNA strands. The parity information associated with a particular short DNA strand is used to correct any errors that occur or are detected during the decoding process. However, if the decoding and error correction processes are not successful using the parity information associated with the particular short DNA strand, global parity information is used to decode the particular short DNA strand and correct the errors. Global parity information includes information from each short DNA strand and the parity information associated with each short DNA strand.

DNA storage error correction code architecture for optimized decoding

A controller memory buffer (CMB) is a portion of volatile memory of a controller of a data storage device that is allocated to a host device for use by the host device. When the CMB is not fully utilized, the controller may determine that at least a portion of the unutilized space of the CMB may be used for non-host data. The at least a portion is based on a number of past workloads and a current workload of the CMB. An amount of available space of the CMB that the controller may utilize is dependent on the number of past workloads and the current workload of the CMB. Thus, the volatile memory of the controller may be more optimally utilized.

Excess CMB utilization by storage controller

During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.

Pre-emptive operations for faster XOR recovery and relocation

Instead of a system with no awareness to the specific properties of the described system files, such as atomicity of different types of system files, utilize the special characteristics of the corresponding system files to optimize storage handling. A host marks a certain logical block address (LBA) range as belonging to an atomic file. That entire range will be treated as a single atomic unit. Conversely, an LBA range being used to append to a log file may have very small atomic units, allowing for incremental updates without changing the atomicity of the rest of the media. When a write command is passed, the write command will have a certain length. Depending on the length of the write command, the device can disassemble the write command into smaller write sectors of the smallest possible write portion. The device will then write the small write portions to a storage location, while keeping an atomic principle of each of the small write portions.

SSD optimization awareness to atomicity of different system files

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Holon, Israel

Alexander Bazarsky