Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Alexander Bazarsky

Ariel Navon

Eran Sharon

Ran Zamir

Yehuda Hahn

Dudy David Avraham

Shay Benisty

Idan Alrod

Omer Fainzilber

Stella Achtenberg

Tomer Tzvi Eliash

Idan Goldenberg

Karin Inbar

Rami Rom

Michael Micha Ionin

Ofir Pele

Alon Marcu

Daniel Joseph Linnen

Yuval Grossman

Michael Ionin

Ishai Ilani

Avichay Haim Hodes

Yoav Markus

Nika Yanuka

William Bernard Boyle

Evgeny Mekhanik

David Rozman

Opher Lieber

Alon Eyal

David Gur

Sergey Anatolievich Gorobets

Nian Niles Yang

Grishma Shah

Jack Frayer

Julian Vlaiko

Tien-Chien Kuo

Tz-Yi Liu

Gadi Vishne

Philip David Reusswig

Tomer Eliash

Ofer Shapira

Joshua Lehmann

Roi Kirshenbaum

Alexander Kalmanovich

Micha Yonin

Itay Busnach

Yan Li

Yu-Chung Lien

Tianhong Yan

Amit Kumar Sharma

Rohit Sehgal

Abhinandan Venugopal

Xinmiao Zhang

Vinayak Bhat

Yan Dumchin

Eyal Sobol

Noam Presman

Yuri Ryabinin

Danny Berler

Mahim Raj Gupta

Arthur Shulkin

A Harihara Sravan

Noga Deshe

Lola Grin

Aki Bleyer

Lior Avital

Yuval Bahar

Lior Bublil

Gilad Koren

David Avraham

Ofer Privman

Tsiko Shohat Rozenfeld

Jonathan Sokolowski

Martin Booth

Sanel Alterman

Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.

Adaptive tuning of memory device clock rates based on usage workloads

A data storage device includes an error correction code (ECC) ordering system that determines a decoding schedule in which two or more flash memory units (FMUs) that have failed an initial decoding process are to be decoded using a joint decoding scheme. The ECC ordering system generates the decoding schedule based on a metric associated with each FMU. The metric on which the decoding schedule is based is a syndrome weight associated with each FMU or is a combined bit error rate (BER) associated with each FMU. When the decoding schedule has been generated, the ECC ordering system causes a joint decoding operation to be executed on the FMUs in the order specified by the decoding schedule.

Optimized decoding scheduling in a joint LDPC and RAID decoding scheme

Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.

Secured failover access through data storage device side channels

A data storage device can generate a recommended read threshold value using a model that was trained under a plurality of conditions. However, such a model may result in an undesirable bit error rate or programming latency. If that should occur, the data storage device can use a different model trained under a condition similar to a current condition of the data storage device. In addition to avoiding an undesirable bit error rate or programming latency, this can result in improved throughput, improved quality of service, and reduced power consumption.

Data storage device and method for using multiple models for predicting a read threshold

A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

System and method for flexible emergency power fail management for multiple persistent memory regions

A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

Data storage device and method for inferring a read threshold using a time tag determination

Examples described herein provide a joint LDPC and XOR (JLX) error correction scheme that utilizes parity of the LDPC code to correct errors in XOR stripes of data, allowing improved protection against error. For example, when decoding of a codeword fails, an XOR operation is performed on the other codewords within the same XOR stripe to generate a copy of the failed codeword. The copy of the failed codeword is used as a soft bit input to an LDPC decoder, providing a sense of where errors in the failed codeword may be situated. The LDPC decoder may then recover the failed codeword. The scrambling seed used for encoding pages of data may also be used for recovering from error in a JLX ECC operation.

Data storage device with joint error correction code engines

A data storage device includes a memory device and a controller coupled to the memory device. When a read threshold calibration operation occurs, less than all of the pages of a representative wordline is sensed, such that read thresholds of less than all of the pages of the representative wordline is obtained. The obtained read thresholds and one or more physical conditions of the representative wordline are provided to a model to obtain the other read thresholds of the remaining pages of the representative wordline that were not sensed. The model correlates read thresholds of one page to another page of the same representative wordline and accounts for the one or more physical conditions of the representative wordline.

Light-weight BES approximation

Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.

Data storage device and method for predicting future read thresholds

A state transition matrix for a data storage system indicates a reliability of data that was read or decoded from a data storage channel. The state transition matrix includes a probability of reading each state of a nucleotide base in an identified storage material when that nucleotide base was initially programmed in a particular state. The state transition matrix is generated by identifying a storage material with the most copies in the data storage system. During a sequencing process, the identified storage material is decoded, corrected and compared against the storage material that was originally synthesized. This information is used to determine the probability values for the state transition matrix. The state transition matrix is provided to an error correction system of the data storage system, which uses the probability information when determining whether decoded data of other storage materials should be corrected.

Generating and using a state transition matrix for decoding data in a DNA-based storage system

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Storage controller having data augmentation components for use with non-volatile memory die

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

Hybrid address translation cache using DRAM

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

Instead of ignoring workflow or priority of tenant, modify the write path according to the tenant behavior and system priority using the multi-tenant storage device. When writing information, the write path usually includes RAM memory where the host or device copies the data. The data is copied to the NVM storage element. The RAM memory may be either part of the storage controller (either SRAM or DRAM) or part of the host (like DRAM in HMB) that may be controlled by the storage controller. The RAM memories are used for different goals by the storage controller and optimizing the overall system performance (write/read) is a priority of the storage device. In multi-tenant architectures, the different tenants may have different priorities to have their requirements fulfilled. The tenant priority is passed by the host to the storage device through an interface and either be static or change dynamically during the device operation. Optimizing the write paths according to tenant workload and priority may be done by a module in the storage controller.

Optimizing usage of multiple write paths on multi-tenant storage devices

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turing Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.

Systems and methods for use with recurrent neural networks

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Holon, Israel

Alexander Bazarsky