U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Intel Corporation

Silicon Hive B.v.

Intel Benelux B.v.

Alexander Augusteijn

Jan Hoogerbrugge

Jeroen Anton Johan Leijten

Edwin Jan Van Dalen

Steven Roos

Orlando Pires Dos Reis Moreira

Martinus C Wezelenburg

Eelco J Dijkstra

Marco Jan Gerrit Bekooij

Willem Charles Mallon

Katarzyna Leijten-Nowak

Bernardo De Oliveira Kastrup Pereira

Paulus M H M A Gorissen

Johan Sebastiaan Henri Van Gageldonk

Joachim Artur Trescher

Hendrik Tjeerd Joannes Zwartenkot

Paul Ferenc Hoogendijk

Wim Feike Dominicus Yedema

Paul A C J Van Loon

Yuanging Guo

Tromp Johannes De Vries

Marcus G A Verhoeven

Jürgen Von Oerthel

Ramon A W Clout

Paul Stravers

Erwan Yann Maurice Le Thenaff

Franciscus J H M Meulenbroeks

Paulus M Gorissen

Fransiscus P Hopmans

A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Packed data alignment plus compute instructions, processors, methods, and systems

Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S), b) initializing a set of removed instructions as empty (S), c) determining the most compact representation of the first set of instructions (S) d) comparing the size of said most compact representation with a threshold value (S), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S), e2) removing said instruction having the highest coding cost from the first set of instructions and (S), e3) adding said instruction to the set of removed instructions (S), f) repeating steps b-f, wherein the first set of instructions is formed by the set of removed instructions (S, S).

Method and apparatus and record carrier

A programmed computer and method are described for generating a processor design. The method carried out by the programmed computer comprises providing an initial model for the processor, specifying a plurality of resources in terms of resource parameters and their mutual relations. Furthermore, statistics are provided indicative of the required use of the resources by a selected application. Thereafter, a reduced resource design is generated by the programmed computer by relaxing at least one resource parameter and/or limiting an amount of resources specified in the initial specification on the basis of the statistics.

Method and apparatus for designing a processor

A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS, IS) arranged for parallel execution of the plurality of instructions; a register file (RF, RF) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV) on the validity of first result data (RD) produced by a first issue slot (IS) and a second identifier (OV) on the validity of second result data (RD) produced by a second issue slot (IS). The communication network comprises at least one selection circuit (SC) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Run-time selection of feed-back connections in a multiple-instruction word processor

A processing system according to the invention comprises a plurality of processing elements (PE, . . . , PE). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU, TU, TU), which task units comprise one processing element (PE) or a cluster of two or more processing elements (PE, PE, PE, PE). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Processing system including a reconfigurable channel infrastructure comprising a control chain with combination elements for each processing element and a programmable switch between each pair of neighboring processing elements for efficient clustering of processing elements

A method is disclosed for partitioning a specification in a source code. In a first step, the specification is converted into a plurality of abstract syntax trees. In a second step, the plurality of abstract syntax trees is partitioned into at least a first set and a second set. The first set of abstract syntax trees is to be implemented by a first processor and the second set of abstract syntax trees is to be implemented by a second processor. The first and second set of abstracts syntax trees are translated to a specification in the original source code language, respectively, allowing the user to add manual changes to the specifications. Furthermore, specific compiler and design tools are used to convert the specifications into corresponding executable machine code and a specification of the co-processor.

Source-to-source partitioning compilation

A threaded interpreter executes a program having a series of program instructions stored in a memory. For the execution of a program instruction the threaded interpreter includes a preparatory unit for executing a plurality of preparatory steps making th program instruction available in the threaded interpreter, and an execution unit with one or more machine instructions emulating the program instruction. The threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions. Machine instructions implement a first one of the preparatory steps for execution in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Method of executing an interpreter program

A VLIW processor comprising: a plurality of functional units (); a distributed register file () comprising a plurality of segments (), the distributed register file () being accessible by the functional units (); a communication unit () for communication with a memory; a communication network () for coupling the functional units () and the distributed register file (); characterized in that the VLIW processor further comprises a spilling device () for transferring data between the distributed register file () and the communication unit ().

VLIW processor with data spilling means

A threaded interpreter ( ) is suitable for executing a program comprising a series of program instructions stored in a memory ( ). For the execution of a program instruction the threaded interpreter includes a preparatory unit ( ) for executing a plurality of preparatory steps making the program instruction available in the threaded interpreter, and an execution unit ( ) with one or more machine instructions emulating the program instruction. According to the invention, the threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions machine instructions implementing a first one of the preparatory steps are executed in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A detector detects whether a same memory location is addressed by a first and second memory address used to access memory for a first and second memory access instruction that are processing at a predetermined relative distance in the pipeline respectively. A correction circuit modifies data handling in a pipeline stage processing the first memory access instruction when the detector signals the addressing of the same memory location and the first and/or second memory access instruction programs a command to compensate said effect of out of order execution of the first memory access instruction with respect to said second memory access instruction.

Data processing device, method of executing a program and method of compiling

A score is computed of how many cache misses occur for the execution of each of a number of blocks. The score is used as a heuristic in a local search in which an original selection is iteratively replaced each time by a selection that differs from the original selection only by the movement of a single block and that has a lower number of cache misses for the sample of execution than the original selection. Thus a selection of locations for placing instructions of a program in main memory is found that minimizes the number of cache misses that occur for a sample of a typical execution of the program.

Method for reducing the frequency of cache misses in a computer

A source program is executed on microcontroller core,of a processing unit,. The core,is capable of native instructions from a predetermined set of micro-controller specific instructions. In a pre-processing step, for the program statements of the source program a program-specific virtual machine is defined with a corresponding set of virtual machine instructions, such that the expression of the program statements in the sequence of instructions requires less storage space compared to using only native instructions. For the program-specific virtual machine an associated conversion means,is defined for converting the program-specific virtual machine instructions into the native instructions of the core,. The source program statements are expressed in a sequence of instructions comprising instructions of the defined virtual machine. The sequence of instructions is stored in an instruction memory,. The conversion means,is represented in the processing unit,. During execution, instructions are fetched from the instruction memory,. The conversion means,is used to convert the fetched virtual machine instructions into native instructions for execution by the core

Converting program-specific virtual machine instructions into variable instruction set

A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organised in an internal directed acyclic graph. A guarding is executed on successor instructions that each collectively emanate from a respectively associated single predecessor instruction. A subset of joined instructions that converge onto a single join/target instruction are then unconditionally joined. This is accomplished by letting each respective instruction in the subset of joined instructions be executed under mutually non-related conditions, specifying all operations with respect to a jump instruction, specifying all operations that must have been executed previously, and linking various basic blocks comprising subsets of successor instructions in a directed acyclic graph which allows parallel execution of any further subset of instructions contained therein.

Method and processor for structuring a multi-instruction computer program in an internal directed acyclic graph

Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for interconnecting the memory and processing facilities, through using a low address field for local addressing, and at least one facultative high address field for extended addressing. In particular, the high address field is provided in a first addressing format as a segment address, and in a second addressing format as containing a RAM/ROM selection bit. More in particular, the high address field can be provided in a third addressing format as containing a RAM/ROM selection bit and a segment address in respective mutually exclusive fields.

Growing community of inventors

Eindhoven, Netherlands

Alexander Augusteijn