International Business Machines Corporation

Alexander Andreopoulos

Dharmendra S Modha

Steven Kyle Esser

Daniel Gruhl

Pallab Datta

Rathinakumar Appuswamy

Michael S Karasick

Jeffrey Alan Kusnitz

Myron Dale Flickner

Andrew S Cassidy

Arnon Amir

Tapan K Nayak

Hirak Jyoti Kashyap

High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware is provided. In some embodiments, a plurality of thermometer codes are received by a neurosynaptic core. The plurality of thermometer codes are split into a plurality of intervals. One of the plurality of intervals is selected. A local maximum is determined within the one of the plurality of intervals. A global maximum is determined based on the local maximum.

High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware

Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.

Low spike count ring buffer mechanism on neuromorphic hardware

High-framerate real-time spatiotemporal disparity mechanisms on neuromorphic hardware are provided. In various embodiments, a first and second spiking input sensor each output a time series of spikes corresponding to a plurality of frames. A neurosynaptic network is configured to receive the time series of spikes corresponding to the plurality of frames; accumulate the time series of spikes in a ring buffer, thereby creating a plurality of temporal scales; for each corresponding pair of frames from the first and second spiking input sensors, determining a mapping of pixels in one of the pair of frames to pixels in the other of the pair of frames based on similarity; based on the pixel mapping, determining a disparity map.

High-frame-rate real-time multiscale spatiotemporal disparity on distributed low-power event-based neuromorphic hardware

Dynamic multiscale routing on networks of neurosynaptic cores with a feedback attention beam and short term memory with inhibition of return is provided. In various embodiments, an input topographic map is received at a spiking neuromorphic hardware system. A saliency map is received, associating a saliency value with each of a plurality of regions of the input topographic map. Based on the saliency map, a first of the plurality of regions in order of saliency value is routed. The first of the plurality of regions is suppressed. Based on the saliency map, a predetermined number of the plurality of regions are sequentially routed in order of saliency value.

Dynamic multiscale routing on networks of neurosynaptic cores

Embodiments of the invention provide a computer-readable medium of visual saliency estimation comprising receiving an input video of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The computer-readable medium further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The computer-readable medium further comprises encoding each map of features extracted as neural spikes.

Extracting motion saliency features from video using a neurosynaptic system

Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.

Detection, tracking and recognition on networks of digital neurosynaptic cores

Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware is provided. In various embodiments, a kernel is divided into a plurality of subkernels. Each subkernel has less than a predetermined size. The plurality of subkernels are distributed, each to one of a plurality of neurosynaptic processors. By each of the plurality of neurosynaptic processors, one of the subkernels is applied to an input to generate a partial convolution. The partial convolutions from each of the plurality of neurosynaptic processors are combined to determine an activation.

Distributed state via cascades of tensor decompositions and neuron activation binding on neuromorphic hardware

Dynamic gating for neuromorphic systems and the configuration thereof are provided. In various embodiments, neurosynaptic system comprises a neurosynaptic core. The neuromorphic core comprises a plurality of neurons and axons. The neurosynaptic core comprises a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal. In various embodiments, a plurality of input parameters are read, defining the behavior of a programmable gate. Based upon the plurality of input parameters, a neurosynaptic core is configured to provide a programmable gate operative to receive a control signal and selectively output a first output signal based on the control signal.

Dynamic gating using neuromorphic hardware

Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.

Scene understanding using a neurosynaptic system

In one embodiment, a system includes one or more electronic neurons and one or more electronic axons. Each neuron is connected to at least one electronic axon via an electronic synapse, and at least one of the one or more electronic neurons is configured to store information in a membrane potential thereof and/or at least one of the one or more electronic axons is configured to store information in an axon delay buffer thereof to act as a memory. In another embodiment, a computer-implemented method includes storing information to a memory comprising electronic neurons and electronic axons. Information is stored in either a membrane potential of at least one of the electronic neurons or in an axon delay buffer of at least one of the electronic axons. Also, each neuron is connected to at least one electronic axon via an electronic synapse.

Short-term memory using neuromorphic hardware

Embodiments of the invention provide a method of visual saliency estimation comprising receiving an input video of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The method further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The method further comprises encoding each map of features extracted as neural spikes.

One or more embodiments provide a neurosynaptic circuit that includes multiple neurosynaptic core circuits that: perform image distortion correction by converting a source image to a destination image by: taking as input a sequence of image frames of a video with one or more channels per frame, and converting dimensions and pixel distortion coefficients of each frame as one or more corresponding neuronal firing events. Each distorted pixel is mapped to zero or more undistorted pixels by processing each neuronal firing event corresponding to each pixel of each image frame. Corresponding pixel intensity values of each distorted pixel are processed to output undistorted pixels for each image frame as neuronal firing events for a spike representation of the destination image.

Lens distortion correction using a neurosynaptic circuit

One or more embodiments provide method for image distortion correction including receiving, by multiple neurosynaptic core circuits, a set of inputs comprising image dimensions and pixel distortion coefficients for at least one image frame via at least one input core circuit. Each distorted pixel is mapped to zero or more undistorted pixels by processing the set of inputs corresponding to each pixel of the at least one image frame by the at least one input core circuit. Corresponding pixel intensity values of each distorted pixel are routed to output undistorted pixels for each image frame via the at least one output core circuit.

Growing community of inventors

San Jose, CA, United States of America

Alexander Andreopoulos