Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Intel Corporation

Alexander Alexandrovich Petyushko

Ivan Leonidovich Mazurenko

Aleksey Alexandrovich Letunovskiy

Dmitry Nicolaevich Babin

Alexander Borisovich Kholodenko

Pavel Aleksandrovich Aliseychik

Denis Vladimirovich Parkhomenko

Meng-Lin Yu

Jian-Guo Chen

Alexander Markovic

Denis Vassilevich Parfenov

Denis Vladimirovich Zaytsev

Yang Han

Anatoli Aleksandrovich Bolotov

Denis Vasilyevich Parfenov

David G Shaw

Alexander Nikolaevich Filippov

Denis Vasilievich Parfenov

Pavel Aleksandrovich Aliseitchik

Denis Vasilevich Parfenov

Dmitry Nikolaevich Babin

An image processing system comprises an image processor configured to construct a designated functional based on a plurality of functions each associated with a corresponding portion of image information relating to at least first and second images, and to generate a target image utilizing the constructed functional. For example, the functions may comprise a set of functions &#x192;(A), &#x192;(A), . . . , &#x192;(A) of pixels from respective input images A, A, Aof the image information, and the functional may be a function F(X) of the set of functions &#x192;,(A) &#x192;(A), &#x192;(A) where X denotes the target image and is generated by minimizing the functional F(X). The input images may be received from one or more image sources and the target image may be provided to one or more image destinations.

Target image generation utilizing a functional based on functions of information from other images

In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.

Incremental preamble detection

A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.

Three-dimensional region of interest tracking based on key frame matching

An image processor comprises image processing circuitry implementing a plurality of processing layers including at least an evaluation layer and a recognition layer. The evaluation layer comprises a software-implemented portion and a hardware-implemented portion, with the software-implemented portion of the evaluation layer being configured to generate first object data of a first precision level using a software algorithm, and the hardware-implemented portion of the evaluation layer being configured to generate second object data of a second precision level lower than the first precision level using a hardware algorithm. The evaluation layer further comprises a signal combiner configured to combine the first and second object data to generate output object data for delivery to the recognition layer. By way of example only, the evaluation layer may be implemented in the form of an evaluation subsystem of a gesture recognition system of the image processor.

Image processor with evaluation layer implementing software and hardware algorithms of different precision

A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.

Test signal generator for low-density parity-check decoder

In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

Preamble detection using vector processors

A machine-implemented method of generating trapping-set information for use in LDPC-decoding processing of read signals generated, e.g., by sensing a storage medium, such as a magnetic platter. In one embodiment, the method can be implemented as an add-on to any other trapping-set search method in which the discovered trapping sets are evaluated to determine their influence on the overall bit-error rate and/or error-floor characteristics of the LDPC decoder. The method can advantageously reuse at least some of the computational results obtained during this evaluation, thereby requiring a relatively small amount of additional computations, while providing a significant benefit of discovering many more trapping sets in addition to the ones that are being evaluated.

Trapping-set database for a low-density parity-check decoder

A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk.

Method for selecting a LDPC candidate code

In one embodiment, an acoustic echo control (AEC) module receives an outgoing signal and an incoming signal, which, at various times, contains acoustic echo corresponding to the outgoing signal. The AEC module has a delay estimation block that estimates, in the time domain, the echo delay using an adaptive filtering technique. This delay estimation is used to align samples of the incoming signal having acoustic echo with the corresponding samples of the outgoing signal from which the acoustic echo originated. The AEC module determines whether or not samples of the incoming signal contain acoustic echo based on the aligned outgoing signal, and the determinations are applied to a hangover counter. The AEC module then suppresses acoustic echo in the incoming signal and adds comfort noise to the incoming signal. The amount of echo suppression performed is gradually increased or decreased based on comparisons of the counter to a hangover threshold.

Time-domain acoustic echo control

An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to synthesize a first vector by filtering a second vector based on a third vector. The second circuit may be configured to (i) generate a gain corresponding to a fourth vector, (ii) compare the gain to a plurality of thresholds and (iii) update the third vector as a function of the gain where the compare determines that the gain is not between the thresholds. The fourth vector may be received from a network as an echo of the second vector.

Fast echo gain change detection

In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.

Chunk-based double-dwell preamble detection

An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a first sample by filtering an input vector based on (a) a filter vector and (b) a stochastic vector. Each of a plurality of components in the stochastic vector generally has a respective random value. The first circuit may also be configured to generate a second sample as a difference between a third sample and the first sample. The third sample may be received from a network as an echo. The second circuit may be configured to update a subset of a plurality of taps of the filtering where a corresponding one of the components of the stochastic vector has a first value of the random values.

Stochastic vector based network echo cancellation

A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Intra-mode prediction for a video transcoder

A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

Accelerator for a read-channel design and simulation tool

A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein motion-vector dispersion observed at the higher spatial resolution is quantified and used to configure the motion-vector search at the lower spatial resolution. For example, for video-frame areas characterized by relatively low motion-vector dispersion values, the motion-vector search may be performed over a relatively small vector space and with the use of fewer search patterns and/or hierarchical search levels. These constraints enable the transcoder to find appropriate motion vectors for inter-prediction coding without having to perform an exhaustive motion-vector search for these video-frame areas, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Growing community of inventors

Bryansk, Russia

Alexander Alexandrovich Petyushko