Cree Gmbh

Cree Research Inc.

Alexander A Suvorov

John Williams Palmour

Ranbir Singh

David Beardsley Slater, Jr

Lori A Lipkin

A monollithic CMOS integrated device formed in silicon carbide and method of fabricating same. The CMOS integrated device includes a layer of silicon carbide of a first conductivity type with a well region of a second conductivity type formed in the layer of silicon carbide. A MOS field effect transistor is formed in the well region and a complementary MOS field effect transistor is formed in the silicon carbide layer. The method of fabrication of CMOS silicon carbide includes formation of an opposite conductivity well region in a silicon carbide layer by ion implantation. Source and drain contacts are also formed by selective ion implantation in the silicon carbide layer and the well region. A gate dielectric layer is formed by deposition and reoxidation. A gate electrode is formed on the gate dielectric such that a channel region is formed between the source and the drain when a bias is applied to the gate electrode. Source drain and body contacts are preferably formed of the same material in a single fabrication step.

Silicon carbide CMOS devices

Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650&deg; C., but preferably more than about 1500&deg;. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500&deg; C. in less than about two minutes. By controlling the ramp-up time, the annealing time and/or temperature and/or the ramp-down time, high performance silicon carbide power devices may be fabricated.

Methods of fabricating silicon carbide power devices by controlled annealing

Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed. Thereby, a p-base may be formed around an n-type source. Lateral and vertical power MOSFETs may be fabricated.

Self-aligned methods of fabricating silicon carbide power devices by

Silicon carbide power devices are fabricated by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. The deep p-type implant and the shallow n-type implant are annealed at less than 1650.degree. C., but preferably more than about 1500.degree.. The annealing preferably takes place for between about five minutes and about thirty minutes. Ramp-up time from room temperature to the anneal temperature is also controlled to be less than about one hundred minutes but more than about thirty minutes. Ramp-down time after annealing is also controlled by decreasing the temperature from the annealing temperature to below about 1500.degree. C. in less than about two minutes. By controlling the ramp-up time, the annealing time and/or temperature and/or the ramp-down time, high performance silicon carbide power devices may be fabricated.

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Durham, NC, United States of America

Alexander A Suvorov