Intel Corporation

Nvidia Corporation

Alex Waizman

Chee-Yee Chung

Don J Nguyen

Tsvika Kurts

James E Breisch

Marcelo Yuffe

Teong Guan Yew

Brian Schieck

Ziv Shmuely

Gurpreet Shinh

Donald E Templeton

Efraim Rotem

Robert L Sankman

Rajiv K Mongia

Michael Zelikson

Bob Sankman

Paul Gauche

A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

Low-impedance power delivery for a packaged die

With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Embedded power gating

Methods and systems provide for a semiconductor die that is compatible with a wide variety of industry standard sockets, where each type of socket is identified by a different pin map. In one embodiment, the die has a plurality of signal lines, one or more surface contacts and one or more signal selectors coupled to the signal lines and the surface contacts. Each signal selector electrically connects one of the signal lines to one of the surface contacts based on a programming signal. In a particularl embodiment, each signal selector includes a multiplexer and a fuse element, where the multiplexer routes one of its input ports to its output port based on a programming value of the fuse element. The programming value can be set by the programming signal.

Programming semiconductor dies for pin map compatibility

A package includes a thermal solution to thermal couple to a semiconductor device to remove heat generated by the semiconductor device, and a device to electrically isolate at least a portion of the thermal solution from the semiconductor device. The package also includes a biasing device to apply a voltage to a body of the semiconductor device.

Method and apparatus for electrical isolation of semiconductor device

Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection during CPU current consumption going from high current to low current consumption. In one approach, a circuit as a power output stage with an output node, and a controller circuit coupled to the power output stage. The controller circuit selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU for a duration proportional to the change in CPU current consumption from high to low current consumption.

CPU surge reduction and protection

A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Resistive element apparatus and method

Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection and increased battery life. In one approach, an integrated circuit as a power output stage with an output node, and a voltage regulator coupled to the power output stage. The voltage regulator selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU.

Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane. A method, according to one embodiment of the invention, includes the calculation of a first characteristic impedance of the dual referenced microstrip transmission line referenced to a primary reference layer, the calculation of a second characteristic impedance of the dual referenced microstrip transmission line referenced to a secondary reference layer, the calculation of an absolute value of a difference between the first and the second characteristic impedance, the comparison of the absolute value of the difference to a predetermined threshold value, and if the absolute value of the difference is greater than the predetermined threshold value, then a physical parameter associated with the characteristic impedance between the primary and secondary reference layers may be varied until the difference is reduced to less than the predetermined threshold. A structure, according to one embodiment of the invention includes a microstrip transmission line, a first conductive plane, a first dielectric layer provided between the microstrip transmission line and the first conductive plane, a second conductive plane, and a second dielectric layer provided between the first conductive plane and the second conductive plane.

Dual referenced microstrip

A power delivery system and a method for setting the parameters of the power delivery system. The effective resistance of the capacitors for each stage may be set to be substantially equal to the effective resistance of the previous stage, and the time capacitive constant of the capacitors may be set to be substantially equal to the effective inductive time constant of the previous stage.

Power delivery system having a plurality of stages and method for setting power delivery system parameters

A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by trace.

Chip package and method

An inverting amplifier having linear output characteristics is disclosed which includes additional n-channel and p-channel transistors coupled to a classic CMOS inverter circuit. The linear transfer characteristic is achieved with nearly full dynamic V.sub.cc range. The invented amplifier yields a linear transfer characteristic by controlling the dimension ratios between each of the transistors. The wide dynamic range, wide bandwidth and low output impedance make the circuit well-suited for use as an output stage of a CMOS operational amplifier.

Growing community of inventors

Zichron Yaakov, Israel

Alex Waizman