Intel Corporation

Alex Thomas

Aaron K Martin

Bryan K Casper

Ganesh Balamurugan

Frank Patrick O'Mahony

Mozhgan Mansuri

Navneet Dour

Roger K Cheng

Ajay Balankutty

Krishnamurthy Venkataramana

Kuan Zhou

Sridhar Tirumalai

Hari Venkatramani

Quoc Nguyen

Christopher P Mozak

Robert J Royer, Jr

Tomer Levy

Noam Lupovich

In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.

Fast self-refresh exit power state

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

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El Dorado Hills, CA, United States of America

Alex Thomas