United Microelectronics Corp.

Novatek Microelectronics Corp.

Alex Tang

Chung-Chien Lu

Ching-Wu Tseng

Frank Chu

Chien-Hung Hsu

Chun-Yi Chou

Chih-Hsin Hsu

Evan Cho

Kuo-Tsai Yen

A source driver, a source driver array, and a driver circuit with the source driver array and a display with the driver are provided in the invention. These devices are improved by receiving a position code signal through a start pulse generating circuit, which also accordingly generate a start pulse. The invention can improve the problem that the highest operation frequency of a flat panel display being restricted by the start pulse and further improve the cost of the conventional display for increasing the operation frequency.

Source driver, source driver array, and driver with the source driver array and display with the driver

A latchable voltage level shifter is provided. The latchable voltage level shifter comprises: a voltage level shifter receiving an original input signal and generating a high voltage signal according to a timing sequence of a first phase control signal; and a high voltage flip-flop, coupled to the voltage level shifter, receiving the high voltage signal and a second phase control signal, the high voltage flip-flop latching the high voltage signal according to a timing sequence of the second phase control signal and outputting a high voltage output signal. The latchable voltage level shifter can be used in a source drive circuit so as to reduce the layout area and production cost.

Source drive circuit

A double waveform method for driving a transmission line at an initial voltage to a final voltage is provided. The method includes finding a first voltage, a first maintenance period for the first voltage, a second voltage and a second maintenance period for the second voltage according to the initial voltage and the final voltage. The first voltage is put on the transmission line for a period equal to the first maintenance period. Thereafter, the second voltage is put on the transmission line for a period equal to the second maintenance period. Finally, the final voltage is put on the transmission line. With this transmission arrangement, a stable and correct signal voltage is transmitted through a transmission line faster.

Double waveform method for driving signals through a transmission line

A voltage level shifter is provided. The shifter includes an AND gate for generating a synchronizing signal according to a periodic signal and a primitive input signal. The synchronizing signal and a first periodic control signal that are in phase with the periodic control signal are inputted to a transistor device. The transistor device is constructed with an inverter. The voltage level shifter further includes a buffer for generating an output signal and a capacitor for storing a signal. The present invention also provides a switching circuit for preventing the turning on of both PMOS transistor and NMOS transistor simultaneously during a switching status. The present invention can also solve the issue caused by the ratio of the channel width to the channel length, thus the uncertainty of the manufacturing process will not affect the circuit. Therefore, the power consumption, the chip area and the cost are reduced.

Voltage level shifter

A security monitoring system with addressable capability is provided. This system allows a plurality of video cameras to be connected to the security guard room via a single cable instead of a plurality of dedicated cables, as in the prior art. The security monitoring system comprises the following: a cable; a central control unit connected at the first end of the cable, capable of issuing a first signal; at least one addressable video camera connected at the second end of the cable connected to the central control unit; and a monitoring device for displaying a second signal. The addressable video camera receives the first signal from the central control unit and compares the first signal with a preset value; if these match, the addressable video camera sends out a second signal via the cable back to the central control unit. This second signal is then displayed on the monitoring device coupled to the monitor. The signal transmission between the central control unit and the plurality of video cameras can be carried out over one single cable. The arrangement and handling of the security monitoring system is therefore considerably simplified.

Addressable security monitoring system

An addressable video camera has an ability to be assigned an address, that allows a security monitoring system utilizing a plurality of such addressable video cameras to be connected to the security guard room via a single cable. The addressable video camera includes the following: a video imaging device for generating a video signal; an amplifier for amplifying the output video signal; a switch connected between the amplifier and the input/output port of the addressable video camera; an address setting unit for presetting an address value to the addressable video camera; a sync signal detector which is capable of generating a demodulation enable signal in response to the received video control signal; a demodulator for demodulating the address signal in the video control signal; and a microprocessor capable of comparing the demodulated address data with the preset address value. If these match, the switch is turned to the conducting state and the video-imaging device is switched to active operation. It then outputs the video signal. Since the signal transmission between the central control unit and the plurality of addressable video cameras can be carried out over one single cable, the arrangement and handling of the security monitoring system is considerably simplified.

Addressable video camera for security monitoring system

A digital filter for time-division multiplexing a set of digital signals has a multiplexer receiving the input signals and selecting one by control signal; a multiplexing digital filter receiving the selected signal and performing a filtering function, which consists of a string of pipeline registers wherein each one delays the input signal a finite time slot; a demultiplexer outputting said filtered signal to one terminal corresponding to the input signal by the same control signal. The method for filtering a set of digital signals matches each digital signal to its own state signals.

Apparatus and method for filtering digital signals

An apparatus for generating pictures comprising a memory device, an address generator, a vertical position detector, a register, a horizontal position counter, a processor and a state machine. Pictures shown in the display are formed based on image parameters stored in the memory device. These parameters are read from memory by controlling the address generator. The parameters read from memory are then processed by the processor before being output to the display. The vertical position detector and the horizontal position counter are provided for controlling the parameter processing. Control signals are generated in the state machine to control the apparatus. By splitting pictures into image cells and skillfully arranging corresponding parameters, colorful pictures with various layer levels are effectively shown in the display.

Generating multilayered pictures by image parameters

An image register for a graphics display includes a pair of static random access memory (SRAM) devices for respectively storing image data associated with even numbered and odd numbered pixels, which correspond to even numbered and odd numbered addresses. The register includes a counter presettable to an initial value corresponding to a starting address of the stored image data. When the counter outputs an even address (an even state), the even SRAM is enabled for a write operation if an input layer code has a higher priority than the priority of the layer code for the image data stored in the even SRAM, although the odd SRAM is always enabled for a read operation in the even state. The read and write operations occur simultaneously. During the read operation on the odd SRAM, the layer code portion of the image data retrieved therefrom is latched in an associated buffer, whose output is fed to an associated comparator. When the counter is incremented during the next clock cycle, the counter outputs an odd address (an odd state), wherein the odd SRAM is enabled for a write operation if an input layer code has a higher priority than the priority of the retrieved layer code buffered from the prior cycle, although the even SRAM is always enabled for a read operation in the odd state. Both operations occur simultaneously. In both the even and odd states, if the priority of the input layer code is not higher than the priority of the layer code associated with the current image data, the original image data is retained in the even and odd SEAMs, respectively.

High-speed image register for graphics display

A high-order oversampling modulation apparatus is disclosed herein. The present invention implements a high-order oversampling modulation apparatus by use of a plurality of shift registers in response to clock signals provided with a frequency higher than the sampling rate in order to simplify the circuit and layout.

Oversampling modulation in a D/A converter using a combination of

An image register for a graphics display includes a pair of static random access memory (SRAM) devices for respectively storing image data associated with even numbered and odd numbered pixels, which correspond to even numbered and odd numbered addresses. The register includes a counter presettable to an initial value corresponding to a starting address of the stored image data. A half adder is coupled to the counter for addressing the SRAMs according to an even and odd state. Two NAND gates responsive to the least significant bit of the counter control the two SRAMs for simultaneously writing image data having a modified color code portion into the even SRAM and reading stored image data from the odd SRAM during an even state, and for simultaneously reading stored image data from the even SRAM and writing the modified color code into the odd SRAM during an odd state. The register includes a pair of full adders to mix an incoming color code with the stored color code to obtain the modified color code. The simultaneous access to consecutive pixels enables parallel processing to occur, thus improving execution speed.

Color mixing device using a high speed image register

A motion video image displaying apparatus and method of displaying is disclosed for displaying multiple fonts of video images in non-DMA mode for television-game machines. The inventive apparatus includes a status controller for generating a number of timing control signals. The apparatus comprises a parameter address generator for producing a parameter address based on the timing control signals and information issued by a CPU of the game machine; a tab address generator for producing a tab address based on the timing control signals, and for producing an overflow signal for the status controller; a color code address generator for producing a color code address based on the timing control signals, information read according to the tab address, and video information. Three tri-state buffers are also included for buffering the address outputs of the parameter address generator, the tab address generator, and the color code address generator, respectively, the buffers are controlled by the status controller to selectively output one of their buffered addresses. A video memory for storing and outputting video information and parameters based on the addresses generated by the parameter address generator, the tab address generator, and the color code address generator is also included.

Method and apparatus for displaying motion video images

A cascaded apparatus of graphic processors for cascading a main graphic processor and at least one secondary graphic processor comprising a clock generator for generating the clock signal to control the timing and synchronize the all the actions; a pixel synchronizer for synchronizing the color codes and layer codes; a layer comparator for comparing the level of layer codes; a mode selector for selecting the mode; a cascade controller for comparing the layer and outputting the color codes; and a color code output device which determines the output of color codes.

Growing community of inventors

Hsinchu, Taiwan

Alex Tang