Virage Logic Corporation

Waferscale Integration, Inc.

Synopsys, Inc.

Waferscale Integration, Incorporation

Alex Shubat

Boaz Eitan

Randall Lee Reichenbach

Chang Hee Hong

Yervant Zorian

Yoram Cedar

Deepak Sabharwal

Reza Kazerounian

Samvel Shoukourian

Gurgen Harutyunyan

Arye Ziklik

Valery Vardanian

John H Pasternak

Karen Amirkhanyan

Hayk Grigoryan

Cuong Trinh

Tatevik Melkumyan

A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

Detecting random telegraph noise induced failures in an electronic memory

A system and method for effectuating a self-timed clock (STC) loop for memory access operations. In one embodiment, the method includes configuring a particular access margin value setting based on configuration data of at least one memory instance of a memory device; and applying the particular access margin value setting to a reference cell assembly associated with the at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for the at least one memory instance.

System and method for providing adjustable read margins in a semiconductor memory

In one embodiment, a computer-implemented system for compiling a fuse assembly for a memory is disclosed. The claimed embodiment comprises: means for defining a memory group including at least one memory instance, each memory instance being characterized by its memory configuration data; means for determining number of fuses required for each memory instance based on its configuration data; means for automatically passing fuse information relating to the number of fuses to a fuse compiler; and means for generating, based on the fuse information, a fuse box assembly having a plurality of fuses organized into a set of fuse segments, each segment corresponding to a particular memory instance of the memory group.

System and method for compiling a memory assembly with redundancy implementation

A system and method for effectuating a self-timed clock (STC) loop for memory access operations wherein an Embedded Test and Repair (ETR) processor engine is utilized for optimizing an access margin value. Upon compiling a semiconductor memory instance based on its configuration data, a default access margin value is passed to a wrapper interface associated with the memory instance. In one implementation, an adjusted access margin value is determined by an optimization algorithm operable to be executed on the ETR processor engine, which adjusted access margin value is used for generating the STC signal with a particular time setting that is optimized for a memory instance of a given size.

An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that includes one or more memory instances, each having corresponding fuse element requirements based on its configuration data. BIST elements and a processor compiler for providing ETR functionality are also specified via suitable portions of the integrated GUI. A fuse equation is employed for computing the number of fuses for each memory instance, which equation is derived based on the memory configuration. Fuse information for each memory instance is automatically passed to a fuse compiler that generates a fuse box having an appropriate number of fuses that can accommodate the fuse requirements of the memory instances of the group.

Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation

A static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. The memory cell is comprised of a pair of cross-coupled inverters. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device.

Radiation-hardened static memory cell using isolation technology

A memory characterization system and method using a hierarchically-stitched netlist generation technique. A plurality of leaf cells forming a memory instance are generated based on a minimum area required to encompass an optimal number of memory strap points relating to global signals that span the memory instance. Input and output pins are defined for each tile with respect to the global signals in both horizontal and vertical directions. A parametric dataset is obtained for each tile using an extractor (wherein the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled by coupling the individual parametric datasets using the input and output pins of the tiles with respect to the global signals.

System and method for memory characterization

A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

System and method for redundancy implementation in a semiconductor device

A semiconductor memory architecture for embedded memory instances having redundancy. A fuse box register is provided outside the memory macro associated with the memory instances. The memory instances are daisy-chained to the fuse box register containing a plurality of fuses used for storing fuse data associated with the defective rows and columns of main memory. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops. The fuse box is then deactivated to eliminate quiescent current through the fuses. The redundancy scan flip-flops, connected in a scan chain, are located inside the fuse box as well as the memory instances. During the shifting mode of operation, the fuse contents are scanned into individual flip-flops, organized as scan registers for row redundancy and column redundancy, of the memory instances. Redundant elements are pre-tested by bypassing the fuses and directly scanning in arbitrary patterns into the redundancy scan flip-flops (override mode operation). The contents of row redundancy scan register (i.e., faulty wordline address information) are compared with an incoming wordline address and if there is a match found, the primary wordline or wordlines are de-selected and the redundant wordline or wordlines are selected.

Architecture with multi-instance redundancy implementation

A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit. The high power unit also includes control transistors for disabling its amplifier and leaker during the standby mode.

Unit for stabilizing voltage on a capacitive node

There is provided an EPROM array including columns of EPROM cells, three types of diffusion bit lines, two types of metal lines and two types of select transistors. The metal lines are formed of metal 1 lines and metal 2 lines, where the metal 1 lines are formed into segmented lines and continuous lines and the metal 2 lines are continuous. The diffusion bit lines are formed of short, medium and continuous lines, where the medium length diffusion lines are associated with one segmented metal 1 line and one metal 2 line, the continuous lines are associated with one continuous metal 1 line and the short bit lines are formed of short segments and are not associated with metal lines. The diffusion lines repeat in the following order: medium length, short, continuous, short. One type of select transistor connects one short diffusion line to one metal 1 line and the second type of select transistor connects one segmented metal 1 line to one metal 2 line. Each column of EPROM cells are located between two neighboring diffusion lines.

Electrically programmable read only memory array

Page logic, which is coupled to a programmable array decoder, allows for expansion of memory address space depending on the number of bits in a page register. The programmable array decoder has a 'don't care' function which allows the user to be independent of the page mode.

Page register with a don't care function

Dummy circuitry, including a dummy input buffer, associated lines, and an additional row in the PLD array, provides an additional input to the PLD to keep the voltage on the bit line low until the correct input signal has fully propagated through the working input buffer and associated lines, thereby preventing a voltage glitch.

Growing community of inventors

Fremont, CA, United States of America

Alex Shubat