Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Other

National University of Singapore

Chartered Semiconductors Manufactured Limited

Alex See

Lap Chan

Randall Cher Liang Cha

Yeow Kheng Lim

Tae Jong Lee

Wei Lu

Wang Ling Goh

Zheng Zou

Kin Leong Pey

Hai Cong

Benfu Lin

Liang Choo Hsia

Yung Fu Chong

Yun Ling Tan

Xuesong Rao

Liang Li

Huang Liu

Lup San Leong

Lei Wang

Chim Seng Seet

Juan Boon Tan

Mei Sheng Zhou

Wanbing Yi

Fan Zhang

Soh Yun Siah

Cher Liang Cha

Feng Chen

Victor Seng Keong Lim

Xiaomei Bu

Kok Hin Teo

Chua Chee Tee

Cher Liang Randall Cha

Hong Yu

Simon Yew-Meng Chooi

Danny Pak-Chum Shum

Ting Cheong Ang

Curtis Chun-I Hsieh

Sang Yee Loong

Pooi See Lee

Jun Song

Yong Kong Siew

Ganesh S Samudra

Chen Feng

Wen Zhan Zhou

Mousumi Bhat

Young-Way Teh

Hyunwoo Yang

Wye Boon Loh

Byung Jin Cho

Peter Hing

Kok Hiang Tang

Chyiu Hyia Poon

Young Seon You

Sneedharan Pillai Sneelal

C K Lau

Siew Yong Kong

Ting-Cheong Ang

Shyue Seng Tan

Jinping Liu

Subhash Gupta

Benjamin Colombeau

Soo Jin Chua

Shyue Fong Quek

Ravi Sundaresan

James Yong Meng Lee

Kheng Chok Tee

Kiat Seng Yeo

Francis Lionel Benistant

Chaw Sing Ho

Kong Hean Lee

Randall Cha

Shijie Wang

Chee Tee Chua

Chuan Chu Wang

David Vigar

Francis YongWee Poh

Yoke Leng Lim

Kho Liep Chok

James Yongmeng Lee

Cheng Yeow Ng

Xiaodong Li

Seng-Keong Victor Lim

Kok Keng Ong

Choon-Beng Sia

Yung Fu Alfred Chong

Fangyue Liu

Boon Kiat Lim

Jane Hui

Ze Xiang Shen

Kwee Liang Yeo

Debora Chyiu Hyia Poon

Cheng Cheh Tan

Binbin Zhou

Changwei Pei

Yeon Kheng Lim

Yong Feng Fu

Siew Yong Leong

Soo Choi Pheng

Lian Choo Goh

Wang Cui Yang

Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.

Integrated two-terminal device with logic device for embedded application

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

Method and device for reducing contamination for reliable bond pads

Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

Methods for removal of hard mask

A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CD). CDis larger than a desired CD (CD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CD.

CD control

Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Integrated circuits with overlay marks and methods of manufacturing the same

Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.

CMP wafer edge control of dielectric

Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

Methods for fabricating integrated circuits with improved active regions

Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Integrated circuits having nickel silicide contacts and methods for fabricating the same

A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F. The width of the patterned second hard mask layers is reduced to a second width Fto form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.

Small pitch and high density contact array

Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.

Integrated circuits with memory cells and methods of manufacturing the same

Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

Planar passivation for pads

A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

CMP head structure with retaining ring

A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

Through silicon vias

Growing community of inventors

Singapore, Singapore

Alex See