International Business Machines Corporation

Alex Richard Hubbard

Cody John Murray

Marc Adam Bergendahl

Alexander Reznicek

Ekmini Anuja De Silva

Sanjay C Mehta

Nelson M Felix

Spyridon Skordas

James John Kelly

James J Demarest

Karen Elizabeth Petrillo

Ryan O Jung

Richard C Johnson

Richard A Johnson

Allan Ward Upham

Nikhil Jain

Vinay Pai

Lawrence Alfred Clevenger

Fee Li Lie

Gauri V Karve

Douglas C La Tulipe, Jr

Kevin R Winstel

In an approach, a processor receives device identification information corresponding to at least one device local to a location of a transaction. A processor receives notification of an infected user. A processor determines that the infected user is associated with the transaction. A processor identifies a second user from the device identification information. A processor sends a notification to the second user.

Contact tracing utilizing device signatures captured during transactions

Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

Secure identification of wafer and chip

A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.

Cognitive system for automatic risk assessment, solution identification, and action enablement

A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.

Dynamic adjustment of post exposure bake during lithography utilizing real-time feedback for wafer exposure delay

A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

Wafer backside particle mitigation

A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a mitigating layer comprising silicon or amorphous carbon; patterning the mitigating layer to form indentations in the mitigating layer; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated and patterned backside mitigating layer; and while maintaining the coated and patterned backside mitigating layer in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.

Wafer bonding misalignment reduction

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Rensselaer, NY, United States of America

Alex Richard Hubbard