Marvell Israel (misl) Ltd.

Alex Pinskiy

Lior Moheban

Yakov Tokar

Gregory Kovishaner

Ronen Goldberg

Yakov Yonai

Eyal Herzog

A method for controlling the flow of data traffic on a destination device in a network involves (a) providing a table associated with the destination device; (b) reading each entry of the table from the start of the table to the end of the table; (c) for each port entry read, determining whether a buffer storage threshold for data received from a source port has been exceeded. When the buffer storage threshold for data received from the source port is determined to have been exceeded, an internal stop message is transmitted to a media access control unit on the destination device, otherwise an internal continue message is transmitted to the media access control unit. Operations (b) and (c) are repeated for each of a plurality of read cycles.

Method and network device for controlling the flow of data traffic

A first-in/first-out (FIFO) buffer includes at least one latch-based FIFO storage line, an input flip-flop stage upstream of the at least one latch-based storage line, an output flip-flop stage downstream of the at least one latch-based storage line. The output flip-flop stage functions as an additional storage line. Clock-gating circuitry separate from the device clock controls timing of the at least one latch-based FIFO storage line, the input flip-flop stage, and the output flip-flop stage. The input flip-flop stage functions as a second additional storage line, or as an input sampling stage. Optional bypass circuitry between the input flip-flop stage and the output flip-flop stage passes data for a storage line directly to the output flip-flop stage, without passing through the at least one latch-based storage line, when the buffer is empty.

Hybrid FIFO buffer

Aspects of the disclosure provide an electronic device. The electronic device can include a first clock gating circuit that is configured to receive a clock signal and selectively transmit a clock pulse of the clock signal when triggered, access circuitry configured to launch configuration data in response to receiving a write request from a management module and trigger the first clock gating circuit to generate a first clock pulse that is delayed by a first predetermined amount of time after the launch of the configuration data by the access circuitry, and a first memory element configured to capture the configuration data in response to receiving the delayed first clock pulse generated by the first clock gating circuit.

Electronic device having relaxed timing constraints for management accesses

Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.

Growing community of inventors

Ashkelon, Israel

Alex Pinskiy