Alcatel Lucent

Nokia Solutions and Networks Oy

Alcatel

Alcatel-lucent USA Inc.

Alex L Chan

Paul J Brown

James Michael Schriel

Daniel Anav

David North

Scott David Dsouza

Charles M Elliott

David Harvey

Paul James Brown

A printed circuit board for mounting electrical components thereupon include: a first side; a second side opposite the first side; electrical connection points disposed on the surface of an exterior edge of the printed circuit board; and wherein the exterior edge of the printed circuit board is between the first side and the second side. Further a method of manufacturing a printed circuit board for mounting electrical components thereupon includes the steps of disposing interconnect structures within the printed circuit board adjacent to at least one edge of the printed circuit board; and removing material from the printed circuit board edge to expose the interconnect structures such that the exposed interconnect structures correspond to a component connection footprint.

Board edge electrical contact structures

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

Array type discrete decoupling under BGA grid

A printed circuit board (PCB) carrier including a multi-layer structure including a plurality of conductive layers and a plurality of insulating layers respectively spaced between the plurality of conductive layers, the multi-layer structure having a footprint corresponding to a large size component of the PCB, and a pocket formed in the multi-layer structure, the pocket configured to receive a discrete component of a size smaller than the large size component.

Discrete component carrier

A printed circuit board (PCB) having a layout aligned with a Ball Grid Array (BGA) package, the PCB including a plurality of victim vias arranged in the PCB, at least one aggressor via arranged in the PCB having a transition with at least one victim via, wherein the transition is a space in the PCB between a victim via and an aggressor via along a row direction or a column direction, and the victim via is not positioned next to more than one transition.

Spatial location of vias in a printed circuit board

Disclosed is a socket apparatus for ball grid array (BGA) balls, including a base member of electrically insulative material, a plurality of electrical contact members disposed in row and column configuration attached to the electrically insulative material, a plate member extending in a row direction, and a plurality of extension members connected to the plate member and configured to press BGA balls of a mounted BGA into the plurality of electrical contact members when the plate member is pulled in a first direction.

Side clamping BGA socket

Disclosed is a socket apparatus for gripping the balls of a ball grid array (BGA), including a base member of electrically insulative material, an array of pairs of electrical contacts disposed in the base member in a configuration corresponding to a terminal ball configuration of said BGA to be mated with the socket apparatus, a first plate member disposed for slidable movement on said base member and having a plurality of parallel extension members extending therefrom and configured to pass through the array of pairs of electrical contacts, a second plate member disposed for slidable movement on said base member and having a plurality of parallel extension members extending therefrom and configured to pass through the array of pairs of electrical contacts, the plurality of parallel extension members of said first plate member disposed between the plurality of parallel extension members of said second plate member, a plurality of insulative nodules disposed on each extension member with nodules forming an array corresponding to said array of pairs of electrical contacts, and the first plate member and second plate member being movable relative to each other on said base member whereby the plurality of insulative nodules urge the corresponding electrical contacts into electrical contact engagement with the balls of a BGA in the socket.

A relieved component pad for 0201 component use between vias on a tight-pitch Ball Grid Array is disclosed herein. The relieved component pad for 0201 component use between vias provides substantially rectangular component pads having a relieved section at a point of closest approach to a via pad. The relieved component pad for 0201 component use is particularly useful for overcoming the problem of 0201 component placement on tight-pitch arrays known in the art.

Relieved component pad for 0201 use between vias

A printed circuit board design for 0204 reverse geometry capacitor use between vias on a tight-pitch Ball Grid Array is disclosed. The printed circuit board design for 0204 reverse geometry capacitor use between vias on a tight-pitch Ball Grid Array provides component landing pads sized to accommodate an 0204 surface mount component within a 1.2 mm by 1.0 mm rectangular spacing. The printed circuit board design for 0204 reverse geometry capacitor use between vias on a tight-pitch Ball Grid Array is particularly useful for overcoming the problem of component placement on tight-pitch arrays known in the art.

0204 shifted vias with merge pads

Disclosed is a printed circuit board (PCB) having backdrill reliability anchors comprising nonfunctional pads to provide mechanical reinforcement for signal pads on backdrilled plated through hole (PTH) vias, as well as associated method and machine readable storage medium.

Backdrill reliability anchors

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

Thermal warp compensation IC package

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

De-pop on-device decoupling for BGA

Embodiments of the invention place surface-mount such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, between BGA pads.

In-grid on-device decoupling for BGA

A land pattern for 1 mm and 0.8 mm pitch arrays has been disclosed for placing two port devices. The land pattern includes a ball grid array (BGA) of BGA pads each connected to a respective through hole via, and a pair of rectangular conductive pads electrically connected to a an adjacent pair of through hole vias, wherein each rectangular pad extends out from its via towards the other via of the pair along a line connecting the centers of said adjacent pair vias. A solder mask is located on the rectangular pad side and has apertures over each rectangular conductive pad. The land pattern is particularly useful for locating two port devices directly underneath a BGA device while minimizing the distance from a BGA ball to the two port device lead.

Land pattern for 0201 components on a 0.8 mm pitch array

Various exemplary embodiments relate to a brace for use with an integrated circuit (IC), and to an IC package with a brace, having a main body portion and a fastening portion for mechanically fastening the main body portion to the IC, by for example clipping or sliding attachment. Other exemplary embodiments relate to a method of stabilizing an IC during an operation carried out on the IC, such as a soldering operation, involving for example steps of attaching a brace to the IC, performing the operation on the IC, and/or removing the brace after performing the operation.

Removable IC package stiffening brace and method

An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of a layer of material bonded to the top of the integrated circuit package. The layer of material may have a generally planar-convex or a generally planar-concave cross-section. By appropriate choice of temperature coefficient and degree of concavity or convexity, the layer of material can compensate for either convex or concave warpage. In some embodiments the layer of material has apertures therein allowing compensation for more complex warpages. The apparatus provides an alternative to apparatus for dealing with IC package warpage known in the art.

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Nepean, Canada

Alex L Chan