Intel Corporation

Alex Kuperman

Harry Muljono

Stefan Rusu

Sunil Kumar

Liang Yin

In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed.

Unidirectional sweep training for an interconnect

A system may include detection of a logical mode of a link port, and changing of a link supply power provided to the link port based on the detected logical mode. Detection of the logical mode may include a determination of whether the link port is terminated by a partner link port. If the link port is not terminated, the link supply power may be reduced to a value that does not preserve logic states of a plurality of link port elements, and, if the link port is terminated, the link supply power may be maintained substantially at V.

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Campbell, CA, United States of America

Alex Kuperman