Taiwan Semiconductor Manufacturing Comp. Ltd.

Stmicroelectronics Gmbh

Alex Kalnitsky

Hsiao-Chin Tuan

Chun-Wen Cheng

Kuei-Sung Chang

Wen-Chuan Tai

Hsiang-Fu Chen

Chia-Ming Hung

Mohammad Al-Shyoukh

Hung-Sen Wang

Harry-Hak-Lay Chuang

Kong-Beng Thei

Chia-Hua Chu

Ruey-Hsin Liu

Chun-Ren Cheng

Chun Lin Tsai

Kuo-Ming Wu

Jiun-Lei Jerry Yu

Chun-Hung Chen

Jun Cai

Yi-Hsien Chang

Hua-Chou Tseng

Chih-Ping Chao

Jye-Yen Cheng

Chih-Wen Yao

Chia-Pao Shu

Chien-Chih Ho

Chia-Yi Su

Wei Tsung Huang

Yuan-Chih Hsieh

Felix Ying-Kit Tsui

Yi-Shao Liu

Chung-Long Chang

Tsung-Yu Yang

Hung-Hua Lin

Allen Timothy Chang

Yi Heng Tsai

Hsin-Li Cheng

Ching-Ray Chen

Jyun-Ying Lin

Jing-Hwang Yang

Yong-En Syu

Liang-Kai Han

Uway Tseng

Yih-Shung Lin

Yung-Chih Tsai

Keng-Yu Chen

Te-Hsi Lee

Emerson Cheng

A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.

Flipped gate voltage reference and method of using

A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.

A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.

Semiconductor device with localized carrier lifetime reduction and fabrication method thereof

A voltage reference includes a flipped gate transistor and a first transistor, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current. The voltage reference further includes a boxing region configured to provide a voltage level at a drain terminal of the first transistor to maintain the first leakage current substantially equal to the second leakage current.

Flipped gate voltage reference having boxing region and method of using

An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.

SiC crystalline on Si substrates to allow integration of GaN and Si electronics

The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate. An optical waveguide structure is located over a first side of the semiconductor substrate at a position over the sensing device. A dielectric structure is disposed onto the optical waveguide structure at a position that separates the optical waveguide structure from a sample retention area configured to receive a sample solution.

Optical biosensor device

A trench metal oxide semiconductor field effect transistor (MOSFET) includes an epitaxial layer over a substrate a first trench in the epitaxial layer and a second trench in the epitaxial layer. A depth of the first trench is different from a depth of the second trench. The trench MOSFET further includes a source region surrounding the self-aligned source contact, wherein the source region is convex-shaped. The trench MOSFET further includes a self-aligned source contact between the first trench and the second trench; wherein the self-aligned source contact is connected to the source region.

Self-aligned contact for trench MOSFET

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

Localized carrier lifetime reduction

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level.

Method to integrate different function devices fabricated by different process technologies

The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Handle wafer for high resistivity trap-rich SOI

A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.

Micro-electro mechanical system (MEMS) structures and methods of forming the same

An integrated semiconductor device for manipulating and processing bio-entity samples is disclosed. The device includes a microfluidic channel that is coupled to fluidic control circuitry, a photosensor array coupled to sensor control circuitry, an optical component aligned with the photosensor array to manipulate a light signal before the light signal reaches the photosensor array, and a microfluidic grid coupled to the microfluidic channel and providing for transport of bio-entity sample droplets by electrowetting. The device further includes logic circuitry coupled to the fluidic control circuitry and the sensor control circuitry, with the fluidic control circuitry, the sensor control circuitry, and the logic circuitry being formed on a first substrate.

Systems and methods for an integrated bio-entity manipulation and processing semiconductor device

Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.

Deep trench structure for high density capacitor

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San Francisco, CA, United States of America

Alex Kalnitsky