Micron Technology Incorporated

Intel Corporation

Alex J Schrinsky

Guangjun Yang

Mohd Kamran Akhtar

Hongbin Zhu

David J Keller

Robert J Hanson

Terry McDaniel

Silvia Borsari

Sanh D Tang

John David Hopkins

Kevin J Torek

Matthew J King

Si-Woo Lee

Anish A Khandekar

Brent D Gilgen

Hongqi Li

Terrence B McDaniel

Niraj B Rana

Jin Lu

Russell A Benson

Scott A Southwick

Chris Larsen

Thy Tran

Pavan Aella

Anton J deVillers

Ronald Allen Weimer

Thomas M Graettinger

Mark W Kiehlbauch

Max F Hineman

Baosuo Zhou

Srinivas Pulugurtha

Christopher J Larsen

Jaydip Guha

Randy J Koval

Vinayak Shamanna

Zishu Zhang

Song Guo

William R Kueber

Saurabh Keshav

Kamal Kumar Muthukrishnan

Yan Li

James B Franek

A method of forming a microelectronic device structure comprises exposing a silicon structure to an etching chemistry at a first bias voltage of greater than about 500 V to form at least one initial trench between sidewalls of features formed in the silicon structure. The method also comprises exposing at least the sidewalls of the features to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench without substantially reducing a height of the features. Related apparatuses and electronic systems are also disclosed.

Microelectronic devices having features with a fin portion of different sidewall slope than a lower portion, and related methods and electronic systems

Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

Integrated assemblies having dielectric regions along conductive structures, and methods of forming integrated assemblies

Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed.

Integrated circuitry, arrays of capacitors of integrated circuitry, and methods used in the fabrication of integrated circuitry

Apparatus, such as electronic devices and structures thereof, include at least one doped surface of a base (e.g., semiconductor) material. A dopant of the at least one doped surface is concentrated along the surface, defining a thickness, on or in the base material, not exceeding about one atomic layer. Methods for forming the doped surfaces involve gas-phase doping exposed surfaces of the base material in situ, within a same material-removal tool used to form at least one opening defined at least partially by the base material and into which the dopant is to be introduced.

Apparatus with doped surfaces, and related methods with in situ doping

Methods of forming integrated assemblies having dielectric regions along conductive structures

A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing an interconnect structure includes forming an opening in a surface of a semiconductor device and forming an interconnect structure at least within the opening. Forming the interconnect structure includes depositing a first insulator material on both the surface and a sidewall of the opening, selectively removing a first portion of the first insulator material on the surface over a second portion of the first insulator material on the sidewall, depositing a second insulator material on the second portion, and depositing a conductive material on the second insulator material. The method further includes selecting the thickness of the first and second insulators materials based on a threshold level of capacitance between the sidewall and the conductive material.

Low capacitance interconnect structures and associated systems and methods

Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.

Semiconductor constructions having peripheral regions with spaced apart mesas

Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.

Methods of forming patterns on substrates

Semiconductor constructions

Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are disclosed.

Methods of forming charge storage structures including etching diffused regions to form recesses

The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O, SOand a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising Oand a gas comprising SOand a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional Oand SOdry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.

Structures comprising masks comprising carbon

Growing community of inventors

Boise, ID, United States of America

Alex J Schrinsky