Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Zhuhai Access Semiconductor Co., Ltd

Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.

Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd.

Alex Huang

Dror Hurwitz

Simon Chan

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Substrates with ultra fine pitch flip chip bumps

A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Polymer frame for a chip, such that the frame comprises at least one via in series with a capacitor

A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one inductor is formed in at least one of the at least one feature layer and the adjacent via layer by electroplating copper into a pattern of photoresist stripping away the photoresist and laminating.

Multilayer electronic structures with embedded filters

A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter; the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.

An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.

Interposer frame with polymer matrix and methods of fabrication

A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.

Embedded packages

An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material.

Chip package

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

Terminations

A multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one copper post that is only partially embedded in an outer layer of dielectric such that part of the at least one copper post protrudes beyond surface of the outer layer of dielectric.

Composite electronic structure with partially exposed and protruding copper termination posts

A multilayer electronic support structure including at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.

Multilayer electronic support structure with integral constructional elements

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and a method of fabrication, the chip sockets are characterized by being rectangular with smooth walls that meet at corners that have radii of curvature of less than 100 microns thereby facilitating a close fit of each socket to the intended chip size, enabling compact chip packaging and miniaturization.

Method of fabricating a polymer frame with a rectangular array of cavities

An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Film bulk acoustic resonator filter

A substrate comprising a capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via a via post standing on said capacitor.

Thin film capacitors embedded in polymer dielectric

A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from a through via at least partway over each chip; dicing the array to create separate dies comprising at least one embedded chip having a contract pad coupled to a through via adjacent the chip.

Growing community of inventors

Zhuhai, China

Alex Huang