Intel Corporation

Fast-chip Incorporated

Other

Alex E Henderson

Walter E Croft

Vishal Sarin

John William Hayes

Raymond M Chu

Linda Elaine Eaton Hayes

Methods and apparatus for the Transporting of Fibre Channel data over Ethernet are disclosed. In one embodiment of the invention, Fibre Channel data frame and primitive signals are transported over Ethernet instead of using the Fibre Channel FC-1 and FC-0 protocols. This allows less expensive Ethernet equipment and devices to transport and perform services for Fibre Channel connected devices without having a physical Fibre Channel interface. The ability to provide Fibre Channel services and functions without having a physical Fibre Channel interface allows existing Ethernet equipment to be placed into service as SAN components without modification.

Transporting fibre channel over ethernet

A services processor includes an editing unit, which performs various functions for editing data packets, such as packet creation, packet encapsulation, and packet replication.

Services processor having a packet editing unit

In a services processor, a queue operations unit controls the output of processed data packets from the services processor. In accordance with a hybrid list/calendar queue priority scheme, the queue operations unit uses a unique data structure comprising a tree of calendar arrays and queue lists to schedule the data packets for output.

Services processor having a queue operations unit and an output scheduler

The invention provides apparati and methods for processing a packet. The processing is done according to a table and context based scheme.

Table driven programming system for a services processor

The invention provides apparatuses and methods for quickly modifying state information. Preprocessing prepares the state information to be modified. A logic unit modifies the state information. Postprocessing then puts the modified state information in proper form for output.

State record processing

A system for filtering data comprises a filtering database for storing layered rule tables and a data filtering engine coupled to the filtering database for filtering the input data using the layered rule tables. The data filtering engine filters or classifies input data using tests or rules performed on the data elements in the input data. The data elements are segments of data in the input data and are selected from the input data using a data element locator. Preferably, each rule table in the filtering database comprises a data element locator, a default rule, and zero or more filtering rules. The filtering rules comprise the tests or rules that are to be applied to the data elements. Each rule table corresponds to a single data element and each filtering rule in the rule table is to be applied to that data element.

System and method for filtering data

A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and cache memory for manipulation and retrieval. A memory subsystem stores packets as linked lists of buffers. Each bank of memory includes a separate memory management controller for controlling accesses to the memory bank. The memory management controllers, a cache management unit, and free list manager shift the scheduling of read and write operations to maximize overall system throughput. For each packet, packet context registers are assigned, including a packet handle that points to the location in memory of the packet buffer. The contents of individual packets can be accessed through the use of encapsulation pointer registers that are directed towards particular offsets within a packet, such as the beginning of different protocol layers within the packet.

System and method for packet storage and retrieval

An apparatus and method for caching data in an associative memory cache using a single non-overlapping entry, wherein the non-overlapping entry is created from a matching entry and one or more overlapping entries that are stored in a primary associative memory.

Caching associative memory using non-overlapping data

A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.

Match resolution circuit for an associative memory

A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.

Boundary addressable memory

A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

Low power wired OR

A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This apparatus reduces, or preferably eliminates, the requirements for application housekeeping, such as garbage collection, by providing substantially more deterministic dynamic memory management operations. Housekeeping, or garbage collection, such as memory compaction and unused space retrieval, are reduced or eliminated. When housekeeping is eliminated, all dynamic memory invocations become substantially deterministic. The invention maps all or a part of a large, sparsely populated logical memory address space used to store dynamically allocated objects, to a smaller, denser physical memory address space. This invention results in a reduction in processing overhead in the computational environment, such as an operating system, which enhances performance, since the application no longer requires housekeeping functions from the environment. This process is particularly applicable to software components developed utilizing object oriented programming, which is more likely to use temporary memory allocation and release, thereby requiring significant housekeeping functions in the prior art.

Eliminating memory fragmentation and garbage collection from the process of managing dynamically allocated memory

A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object manager for managing the memory objects used by the host processor. The object manager may further comprise an address translation table for translating virtual space addresses for memory objects received from the host processor to physical space addresses for memory elements, and a management table for storing data associated with the memory objects used by the host processor.

Caching dynamically allocated objects

A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input signal from the second rail of the dual rail driver. In one embodiment, the input signal from the first rail of the dual rail driver can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0.18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from GROUND to 400 MV.

Dual rail drive for distributed logic

A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the search client for generating a matching signal; and a associative memory element coupled to the caching associative element configured to search for data not stored in the caching associative memory element. The search client issues a search request for data to associative cache element. If the matching data is found there, then such matching data is returned to the search client. Alternatively, if the data is not found, then the search request is issued to the main associative memory. The least frequently used data or the least recently used data in the associative memory cache are replaced with the matching data and the higher priority data.

Growing community of inventors

Hillsborough, CA, United States of America

Alex E Henderson