Qualcomm Incorporated

Alex Dongkyu Park

Sei Seung Yoon

Esin Terzioglu

Venkatasubramanian Narayanan

Balachander Ganesan

Changho Jung

Francois Ibrahim Atallah

Keith Alan Bowman

Venugopal Boynapalli

Bilal Zafar

Kashyap Ramachandra Bellur

Shahzad Nazar

Prabaharan Balu

An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Scannable memories with robust clocking methodology to prevent inadvertent reads or writes

A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Aging sensor for a static random access memory (SRAM)

In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage Vfor the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage V.

Read operation based aging sensor for static random access memory (SRAM)

A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Global reset with replica for pulse latch pre-decoders

Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.

Growing community of inventors

San Diego, CA, United States of America

Alex Dongkyu Park