Arm Limited

Alex Beharrell

Andrew John Merritt

Raghavendra Adiga Bandimutt

Saqib Rashid

There is provided an apparatus that includes a first port that receives first data of a first type from a first storage circuit. A second port receives second data of a second type from a second storage circuit having a lower worst case latency in hardware than the first storage circuit. A third port receives access requests for the first data and the second data from a processing circuit. When one of the access requests is received for the first data, it is forwarded to the first storage circuit and when the one of the access requests is received for the second data, it is forwarded to the second storage circuit. A shared storage circuit stores the first data and the second data and has a storage capacity.

Storing data from low latency storage

Apparatuses and methods of operating apparatus are disclosed. A processing element performs data processing operations with respect to data items stored in data storage. In a first mode the processing element references the data items using physical addresses and in a second mode the processing element references the data items using virtual addresses. A data access request handling unit receives data access requests issued by the processing element and cache stores cache lines of temporary copies of the data items retrieved from the data storage, wherein a cache line in which a data item is stored in the cache is selected in dependence on an address index portion. The data access request handling unit is responsive to a data access request for the data item from the processing element in the second mode to determine an index matching condition to be true when the address index portion of the physical address of the data item matches the address index portion of the virtual address of the data item and, when the index matching condition is false, to prevent allocation of the data item into the cache.

Growing community of inventors

Cambridge, United Kingdom

Alex Beharrell