Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Alessandro Torielli

Marco Gandini

Luigi Licciardi

Maura Turolla

Gianmario Bollano

Mauro Marchisio

Pierangelo Garino

Andrea Finotello

Frederich Mombers

Marco Mattavelli

Martin Gumm

Stephanie Dogimont

Didier Nicoulaz

Fabio Bellifemine

A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration. circuits (CT,. . . CT,, WR, SR; CT,. . . SR,, CT,. . . SR,) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing (FIG.,).

Content addressable memories

Circuit for motion estimation in digitized video sequence encoders

The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.

CMOS cell for logic operations with fast carry

The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are controlled by an auxiliary fast logic allowing their performance to be extended to the other operations. The unit also has a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.

C-MOS arithmetic - logic unit with high carry propogation speed

The circuit comprises two registers (SR12, SR8) which temporarily memorize uncompressed and compressed PCM words, respectively. The uncompressed word is sequentially read and a counter (CNT) counts the number of zeroes present in the most significant positions of the absolute value of the word. The compressed word is composed, in the corresponding register, of the sign bit of the uncompressed word, followed by the counting bits of the counter and by the bits of the positions of the uncompressed word following those of the counted zeroes.

PCM compression by encoding runs of zeroes

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Turin, Italy

Alessandro Torielli