Qualcomm Incorporated

Stmicroelectronics Gmbh

Alessandro Risso

Li Feng Zhang

Afshin Haftbaradaran

Shravan Kumar Reddy Garlapati

Sivagnanam Parthasarathy

Hari Sankar

Mustafa Nazmi Kaynak

Patrick Robert Khayat

Alexandre Pierrot

Cunzhen Liu

Hobin Kim

Ming Lin

Lun Bin Huang

Harsha Narasimha Acharya

Alexei Yurievitch Gorokhov

Gabi Sarkis

Ashok Mantravadi

Subramanya P Rao

Jae Ho Ryu

Dillip Kumar Dash

Chinmay Shankar Vaze

Omar Mehanna

Erman Koken

An apparatus for wireless communication is provided. The apparatus may be a receiver device that includes an error correction decoder, such as a low-density parity check (LDPC) decoder. The apparatus may achieve power savings and/or operation cycle savings by disabling the error correction decoder in scenarios where bits of a codeword in a signal transmission are received without errors. The apparatus obtains a first set of bits of a codeword, wherein the codeword includes the first set of bits and a second set of bits, and wherein the second set of bits is punctured. The apparatus recovers the second set of bits based on at least the first set of bits and determines whether to operate an error correction decoder based on a result of an error detection operation performed on the codeword using the first set of bits and the second set of bits.

Control of error correction decoder operation and usage in a receiver device

An apparatus may be configured to receive a polar-encoded transmission comprising at least one intermediate node associated with a first configuration of frozen leaf nodes and information leaf nodes. The apparatus may further be configured to apply an FHT to a first set of values associated with a first intermediate node of the at least one intermediate node to generate a second set of values associated with the first intermediate node. The apparatus may also be configured to select, based on the second set of values, one or more paths associated with the first intermediate node for a SSCL decoding. The apparatus may further be configured to calculate a path metric for each of the selected one or more paths associated with the first intermediate node.

Polar coding Reed-Muller node optimization using Fast Hadamard Transform

Methods, systems, and devices for wireless communications are described. A shared channel may include a set of tones carrying multiple types of control information multiplexed together. A wireless device may perform a tone classification method to determine individual subsets of tones from the set of tones for each type of control information to extract each type of control information. The wireless device may determine multiple subsets of tones correspond to multiple types of control information simultaneously based on different extraction parameters. For example, the wireless device may determine a total number of tones in a set of tones, a distance between any given two tones in the set of tones, an offset value, or any combination thereof for the extraction parameters. The wireless device may then use these extraction parameters to determine or extract two or more subsets of tones for two or more corresponding types of control information.

Tone classification for physical channels with multiplexed data

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a receiving node may determine a cyclic redundancy check (CRC) based at least in part on log-likelihood ratios (LLRs) associated with downlink control information (DCI) received from a transmitting node. The receiving node may perform a full unmasking of the CRC using a radio network temporary identifier (RNTI) based at least in part on a descrambling of the CRC with the RNTI, wherein a number of bits associated with the RNTI is associated with a number of bits associated with the CRC. The receiving node may initiate an early termination of a decoding of the LLRs based at least in part on the full unmasking of the CRC. Numerous other aspects are described.

Techniques for masking and unmasking cyclic redundancy check bits for early termination of decoding

An apparatus (e.g., receive chain) for wireless communications may perform de-interleaving, de-rate matching, and hybrid automatic repeat request (HARQ) combining in a single step. The apparatus may include a data pool configured to store HARQ log likelihood ratio (LLR) data from previous transmissions. The apparatus may include a HARQ onload controller configured to load HARQ LLR data from the HARQ data pool into a HARQ buffer. The apparatus may include an LLR buffer configured to store received demodulated, interleaved, and rate matched LLR data. The apparatus may include a plurality of processing engines configured to, starting at different locations of the LLR buffer: receive new input data from the LLR buffer; combine the HARQ LLR data from the HARQ buffer with the new input data to generate de-interleaved, de-rate matched, and HARQ combined data; and write the de-interleaved, de-rate matched, and HARQ combined data into the HARQ buffer.

Single step in-place operation method for 5G NR de-interleaving, de-rate matching, and HARQ combination

Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.

Error detection for a wireless channel

Aspects described herein relate to decoding downlink control information (DCI) based on multiple DCI sizes. A first hypothesis of multiple hypotheses for decoding a communication received in a control channel search space, wherein the multiple hypotheses are based on different corresponding DCI sizes can be determined. The communication received in the control channel search space can be decoded based on the first hypothesis. For each of the multiple hypotheses and based on the different corresponding DCI sizes, information bits can be extracted from the communication as decoded. For each extracting of the information bits, cyclic redundancy check (CRC) can be performed based on one of the different corresponding DCI sizes to determine whether extracting of the information bits yields DCI.

Techniques for decoding downlink control information with different sizes in wireless communications

Certain aspects of the present disclosure generally relate to techniques for combining a plurality of decision metrics of a scrambled payload in a 5G wireless communications system. For example, in some cases, combining decision metrics of a scrambled payload may generally involve receiving a first payload at a receiver that was scrambled both before and after encoding, generating a second payload at the receiver with selectively set payload mask bits, and using the selectively-set payload mask bits in the second payload to descramble the first payload.

Combining decision metrics of a scrambled payload

In an aspect, a method of encoding data for transmission includes reading, for a block of encoded data on which interleaving and rate-matching is to be performed, the block of encoded data from a buffer, by first and second interleaving and rate matching engines operating in parallel and, starting at first and second starting points of the buffer, respectively. Encoded output data includes the interleaved and rate matched data from both engines. In another aspect, a method of decoding received data includes reading data of a log likelihood ratio (LLR) buffer, by first and second de-interleaving and de-rate matching engines, starting at first and second starting points of the LLR buffer, respectively. Decoded output data includes de-interleaved and de-rate matched data of both engines.

On the fly interleaving/rate matching and deinterleaving/de-rate matching for 5G NR

A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method

An embodiment of a data write path includes encoder and write circuits. The encoder circuit is configured to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is configured to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.

Rendering data write errors detectable

An embodiment of a data read path includes recovery and decoder circuits. The recovery circuit is operable to recover coded data from a storage medium, and the decoder circuit is operable to detect, in the recovered data, a write error that occurred during a writing of the coded data to the storage medium. For example, such an embodiment may allow detection of a write error that occurred while writing data to a bit-patterned storage medium.

Detecting data-write errors

Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method

A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

System and method for map detector for symbol based error correction codes

A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.

Growing community of inventors

San Diego, CA, United States of America

Alessandro Risso