Stmicroelectronics S.r.l.

Alessandro Moscatelli

Giuseppe Croce

Alessandra Merlini

Claudia Raffaglio

Bruno Murari

Paola Galbiati

Mauro Colombo

M Paola Galbiati

Carlo Masseroni

Lorenzo Labate

A method of operating a Power Line Communications (PLC) network including a plurality of nodes having wirelines extending therebetween for propagating PLC signals between said nodes over said wirelines. The method includes coupling to a set of nodes of the PLC network respective partitioning filters, which can be activated for countering propagation of the PLC signals through the nodes to which said partitioning filters are coupled. The method also includes selectively activating filters chosen from among said partitioning filters, so that said PLC network is partitioned into a plurality of sub-networks with the propagation of PLC signals between the various sub-networks countered by the activated partitioning filters.

Method of operating communication networks, corresponding communication network and computer program product

A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor region, a source comprising a first highly doped portion aligned with the gate electrode and a drain comprising a lightly doped portion aligned with the gate electrode and a second highly doped portion included in the lightly doped portion. The process forms on the lightly doped portion, a protective layer of a first material; forms on the lateral MOS transistor, a dielectric layer of a second material selectively etchable with respect to the first material; forms, in the dielectric layer first, second, and third openings; and fills the openings with a conductive layer that forms drain and source contacts electrically connected to the first and second highly doped portions, and one electrical shield substantially aligned with the protective layer.

Manufacturing process for lateral power MOS transistors

A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Method for manufacturing a MOS transistor

A power amplifier comprising at least a load element and at least an active element inserted, in series to each other, between a first and a second voltage reference is described. Advantageously, according to an embodiment of the invention, the load element comprises a DMOS transistor.

Cascoded power amplifier, particularly for use in radio frequency

A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors. The gate region of the vertical or lateral transistors is then covered with a protective layer. A low-resistance layer is then formed on the gate regions of the CMOS transistors.

Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate

MOS transistor

A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods

An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Growing community of inventors

Como, Italy

Alessandro Moscatelli