International Business Machines Corporation

Alessandro Marchioro

Kin Shing Chan

Chiao-Mei Chuang

Sang Hoo Dhong

Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor

A fast adder/subtracter using a decoder and shifting function instead of conventional full-adders is disclosed. The circuit is optimized for the addition of multiple operands up to 4-5 binary bits in magnitude. Using this method a subtraction operation can be performed at no added cost with respect to addition (compared to the conventional method requiring complementing one of the operands). Addition and subtraction of multiple operands is implemented by simple multiple shift operations. The multiple shift operations can be implemented as a chain of series NMOS pulldown devices with a precharged load providing considerable speed advantage over conventional solutions. Fast overflow detection may be implemented by or-ing the higher order bits in the shifter.

Fast multiple operands adder/subtracter based on shifting

In order to access several pieces of information concurrently, computers can make use of multi-port access memories. This invention introduces a circuit for a memory system that can be used in such applications. Dual-ported memory access is achieved without duplication of the memory arrays or of the word and bit lines used in the circuit. The circuit allows concurrent read and/or write operations by controlling access to independently controlled sections of the word lines in a memory array and is useful for dual ported data caches. In instruction cache memory applications, the circuitry can be used to allow concurrent access to a number of multiple words. The total number of words accessed concurrently is equal to the total cache width and is independent of the address of the lowest word being accessed.

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Ferney Voltaire, France

Alessandro Marchioro