Micron Technology Incorporated

Other

Stmicroelectronics S.r.l.

Alessandro Grossi

Marcello Mariani

Roberto Bez

Giorgio Servalli

Paolo Giuseppe Cappelletti

Anna Maria Conti

Giulio Albini

Cesare Clementi

Federica Zanderigo

Paolo Tessariol

Angelo Visconti

Roberto Gastaldi

Emilio Camerlenghi

Carlo Cremonesi

Tecla Ghilardi

A method of forming an array of gated devices includes forming trenches between walls that longitudinally extend in rows and project elevationally from a substrate. The walls comprise semiconductor material. Gate dielectric is formed within the trenches laterally over side surfaces of the walls and conductive gate material is formed within the trenches laterally over side surfaces of the gate dielectric. Side surfaces of an elevationally inner portion of the gate material within the trenches are laterally covered with masking material and side surfaces of an elevationally inner portion of the gate material within the trenches are laterally uncovered by the masking material. The elevationally outer portion of the gate material that is laterally uncovered by the masking material is removed while the side surfaces of the elevationally inner portion of the gate material are laterally covered by the masking material to form gate lines within the trenches laterally over elevationally inner portions of the walls.

Methods of forming an array of gated devices

A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally from a substrate and spaced from one another along rows and columns. A gate line is formed laterally proximate each of two opposing sidewalls of the blocks along individual rows of the blocks. After forming the gate lines, semiconductor material of the blocks is removed laterally between the gate lines to form pairs of pillars from the individual blocks that individually have one of the gate lines laterally proximate one of two laterally outermost sidewalls of the pair and another of the gate lines laterally proximate the other of the two laterally outermost sidewalls of the pair. Other methods are disclosed.

In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

Shallow trench isolation for a memory

In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.

Flash memory having multi-level architecture

Subject matter disclosed herein relates to a multi-layer memory, and more particularly to operating same.

Multi-layer flash memory

A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

Process for self-aligned manufacture of integrated electronic devices

In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area () is delimited in a semiconductor wafer (). At least one resistive region () having a predetermined resistivity is then formed in the active area (). Prior to forming the resistive region (), however, a delimitation structure () for delimiting the resistive region () is obtained on top of the active area (). Subsequently, protective elements () are obtained which extend within the delimitation structure () and coat the resistive region ().

Process for manufacturing integrated resistive elements with silicidation protection

A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

Reference cell layout with enhanced RTN immunity

Self-aligned integrated electronic devices

A method manufactures non-volatile memory devices integrated on a semiconductor substrate and including a matrix of non-volatile memory cells and associated circuitry. The manufacturing method includes: forming a plurality of electrodes of the matrix memory cells, each electrode including a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer; and forming a plurality of electrodes of transistors of the circuitry each including a first dielectric layer and a first conductive layer. The method also includes forming first coating spacers on the side walls of the gate electrodes of the memory cell and second coating spacers on the side walls of the gate electrodes of the circuitry, the second spacers being wider than the first spacers.

Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate

In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area () is delimited in a semiconductor wafer (). At least one resistive region () having a pre-determined resistivity is then formed in the active area (). Prior to forming the resistive region (), however, a delimitation structure () for delimiting the resistive region () is obtained on top of the active area (). Subsequently, protective elements () are obtained which extend within the delimitation structure () and coat the resistive region ().

Integrated resistive elements with silicidation protection

A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Growing community of inventors

Milan, Italy

Alessandro Grossi