United States of America As Represented by the Administrator of Nasa

The United States of America As Represented by the Administrator of the

Alessandro D Geist

David J Petrick

Thomas P Flatley

Nicholas Franconi

Christopher Wilson

Cody Brewer

Gary A Crum

Robin A Ripley

Manuel Buenfil

Daniel C Espinosa

Austin Lanham

Michael R Lin

Gary R Crum

Travis Wise

Alan Gibson

Jeffrey C Hosler

Jonathan Boblitt

Software and hardware for monitoring, testing, and developing communication and electronic systems on spacecrafts. Several systems are provided to monitor, test, and control a next generation SpaceCube, including a RadHard Monitor (RHM), a Mini ASTM Board, an FMC+ ASTM Board, a Mini Evaluation Board, a MEZZ and an Automated Test Suite. The RHM are FPGA IP and hardware configured to monitor COTS components. The Mini ASTM Board connects a Mini Processor Card to an ASTM for electrical testing. FMC+ ASTM Card connects FMC and FMC+ test cards to the ASTM for electrical testing. A Mini Evaluation Board supplies all necessary power to the Mini Processor card. The MEZZ is a multi-use GSE test board that is compatible with several different development platforms in the SpaceCube to allow developers to develop and test their software. The Automated Test Suite provides functional testing of an assembled SpaceCube board.

Test, development and deployment infrastructure for spacecube high-performance flight processors

The present invention relates to a single-board solid state data recorder (SSDR) card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, which includes: a field programmable gate array (FPGA): a plurality of NAND storage banks of non-volatile NAND Flash storage, the plurality of NAND storage banks which store operational data, each of which is controlled by a NAND Flash controller which controls the signaling of the plurality of NAND storage banks and reading and writing to the plurality of NAND storage banks; and a plurality of SpaceWire nodes and a plurality of multi-gigabit transceivers which command the SSDR card and read/write data to the SSDR card; wherein the plurality of NAND Flash memory banks is independently controlled and independently powered.

Solid state data recorder (SSDR) for use with form-factor avionics systems

The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Processor card and intelligent multi-purpose system for use with processor card

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards

A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm&#xd7;7 cm.

SpaceCube V2.0 micro single board computer

A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Radiation-hardened processing system

Growing community of inventors

Bethesda, MD, United States of America

Alessandro D Geist