Sgs-Thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Alessandro Cremonesi

Franco Cavallotti

Rinaldo Poluzzi

Danilo Pietro Pau

Daniele Alfonso

Carla Maris Golla

Fabrizio Airoldi

Fabrizio Basso

Gianguido Rizzotto

Emiliano Mario Piccinelli

Luca Celetto

Andrea Graziani

Giulio Frigerio

Gian G Rizzotto

Marco Bianchesi

Sandro Delle Feste

A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.

Process for changing the resolution of MPEG bitstreams, and a system and a computer program product therefor

In order to generate, starting from an input MPEG bitstream, an output MPEG bitstream having at least one entity chosen among syntax, resolution, and bitrate modified with respect to the input bitstream, first portions and second portions are distinguished in the input bitstream, which respectively substantially do not affect and do affect the variation in bitrate. When at least one between the syntax and the resolution is to be modified, the first portions of the input bitstream are subjected to the required translation, then transferring said first portions subjected to syntax and/or resolution translation to the output bitstream. When the resolution is left unaltered, the second portions are transferred from the input bitstream to the output bitstream in the substantial absence of processing operations. When the resolution is changed, the second portions of the input bitstream are subjected to a filtering in the domain of the discrete cosine transform.

Process for changing the syntax, resolution and bitrate of MPEG bitstreams, a system and a computer product therefor

The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic. The output of each read amplifier corresponding to the most significant bit of each value is connected to the corresponding input bit line of the associated adder and to all the other most significant input bit lines.

Memory for programmable digital filter

A method of filtering digital signals having a high dynamic range includes splitting the sampled input signal into at least two portions addressing each of the portions to a respective program filter, and performing each filtering operation in parallel and independently, and reconstituting an output signal by summing together the digital outputs from each filter.

Method and apparatus for filtering digital signals

An oversampling digital filter with Finite Impulse Response is implemented using a serial structure having a memory for the coefficients, a memory for the signal samples to be filter, a multiplier connected to the output of the memories, an accumulator connected to the output of the multiplier, and a simple control unit which controls these elements according to an input clock signal.

Filtering method and digital over sampler filter with a finite impulse

The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.

Method and apparatus for filtering high resolution digital signals

An electronic device for the automatic conversion of sampling frequencies, being a type adapted to convert a predetermined frequency of a sampled input signal to a desired frequency of an output signal. The device is comprised of: a phase detector being input both the input frequency and the output frequency; a decoder block associated with the detector to determine an interpolation coefficient; an interpolation filter having a digital input for encoding the sampling signal and receiving the input frequency on the one side, and a digital signal representative of the interpolation coefficient on the other side; and a synchronizer connected after the filter and being input both said input and output frequencies, the synchronizer having a digital output for encoding the converted sampling signal.

Electronic device for the automatic conversion of sampled frequencies

A programmable device for storing digital video lines, being of a type intended for use in TV sets with digital frame scan features whereby a video line is sample coded in a digital signal, comprises at least one pair of memories each adapted to contain the code of one video line, and a bank of registers connected in series to one another and to each of the memories, at least one of the registers being fed, at its input terminals, with the digital signal to parallel the samples to be input to the memories.

Programmable device for storing digital video lines

The invention relates to a method for reducing noise of the pulsive type in digital video receiver sets. The method consists of picking up a noise-affected sample of a video signal and replacing it with a weighted average of samples located in the contour thereof; this allows the noise component to be fittered out with a lower load, in terms of circuit complexity, on the TV set.

Method and an apparatus for reducing noise of the pulsive type in

The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.

Programmable digital filter

A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

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S. Angelo Lodigiano, Italy

Alessandro Cremonesi