International Business Machines Corporation

Tokyo Electron Limited

Globalfoundries Inc.

Alessandro Cesare Callegari

Vijay Narayanan

Sufi Zafar

Sampath Purushothaman

Michael Abramovich Gribelyuk

Dianne L Lacey

Fuad Elias Doany

Vamsi Krishna Paruchuri

Fenton Read McFeely

Paul Charles Jamison

Praveen Chaudhari

Katherina E Babich

James Patrick Doyle

James Andrew Lacey

Katherine Lynn Saenger

Michael Patrick Chudzik

Christopher Vincent Jahnes

Evgeni Petrovich Gousev

Deborah A Neumayer

Shui-Chih Alan Lien

Douglas Andrew Buchanan

Eileen Ann Galligan

Bruce Bennett Doris

Jane M Shaw

Michelle Leigh Steen

Stephen Alan Cohen

Alfred Grill

Cyril Cabral, Jr

Eduard Albert Cartier

Minhua Lu

Rajarao Jammy

Vishnubhai Vitthalbhai Patel

James L Speidell

David L O'Meara

Christopher Peter D'Emic

Stephan Alan Cohen

Cory Wajda

Kristen Scheer

Eugene John O'Sullivan

Martin Michael Frank

Gareth Geoffrey Hougham

Alan Edward Rosenbluth

Tze-Chiang Chen

Anthony I Chou

Barry P Linder

Naftali Eliahu Lustig

Harold John Hovel

Edward William Kiewra

Yanning Sun

Anthony Dip

Mahesh Govind Samant

David Earle Seeger

John Patrick Hummel

Zhihong Chen

Alessandro Curioni

John Jacob Yurkas

Kei-Hsiung Yang

John J Ritsko

Teresita Ordonez Graham

Leena Paivikki Buchwalter

Pushkar Ranade

James Henry Glownia

Hyungjun Kim

Young-hee Kim

Andrew T Pomerene

Wanda Andreoni

Donis G Flagello

Theodore Harold Zabel

Paul J Higgins

Fred Buehrer

Shui-Chin Alan Lien

Joachim Stohr

Carlo A Pignedoli

Devendra K Sadana

Josephine B Chang

Michael A Guillorn

Ying Di Zhang

Praneet Adusumilli

Kenneth Parker Rodbell

Paul Stephen Andry

Supratik Guha

Kuen-Ting Shiu

Renee Tong Mo

Christos Dimitrios Dimitrakopoulos

Dae-Gyu Park

John Christopher Arnold

Hiroki Nakano

Joseph Francis Shepard, Jr

Ko-Tao Lee

Harald F Okorn-Schmidt

Christopher D Sheraw

Edward D Babich

Stephen L Brown

Tsuyoshi Takahashi

Ricky S Amos

Changhwan Choi

Glenn A Biery

Richard Allen John

Joseph S Newbury

Yoshimine Kato

A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer on a substrate, the insulating layer having a top surface; forming a via in the insulating layer; forming an active metal layer over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via.

Selective nanotube growth inside vias using an ion beam

Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

Method to improve nucleation of materials on graphene and carbon nanotubes

A device and method for fabricating a capacitive component includes forming a high dielectric constant material over a semiconductor substrate and forming a scavenging layer on the high dielectric constant material. An anneal process forms oxide layer between the high dielectric constant layer and the scavenging layer such that oxygen in the high dielectric constant material is drawn out to reduce oxygen content.

Dielectric equivalent thickness and capacitance scaling for semiconductor devices

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.

Filling narrow openings using ion beam etch

A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Field-effect transistor device having a metal gate stack with an oxygen barrier layer

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

High performance CMOS circuits, and methods for fabricating same

A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000&#xb0; C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 &#x212b; in a p-metal oxide semiconductor (pMOS) device.

[object Object]

The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800&#xb0; C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8&#xd7;10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0&#xd7;10inversion charges/cmor greater.

Method of forming metal/high-&#x3ba; gate stacks with high mobility

A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

Dual metal gate self-aligned integration

A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO, AlOand other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000&#xb0; C. A low temperature/low pressure CVD technique with Re(CO)as the source material is used when Re is to be deposited.

High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.

Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode

A compound metal comprising MONwhich is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the MONcompound metal. Furthermore, the MONmetal compound of the present invention is a very efficient oxygen diffusion barrier at 1000&#xb0; C. allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 &#x212b; in a p-metal oxide semiconductor (pMOS) device. In the above formula, M is a metal selected from Group IVB, VB, VIB or VIIB of the Periodic Table of Elements, x is from about 5 to about 40 atomic % and y is from about 5 to about 40 atomic %.

Metal oxynitride as a pFET material

Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.

Method for composition control of a metal compound film

A method of fabricating a dielectric film comprising atoms of Si, C, O and H (hereinafter SiCOH) that has improved insulating properties as compared with prior art dielectric films, including prior art SiCOH dielectric films that are not subjected to the inventive deep ultra-violet (DUV) is disclosed. The improved properties include reduced current leakage which is achieved without adversely affecting (increasing) the dielectric constant of the SiCOH dielectric film. In accordance with the present invention, a SiCOH dielectric film exhibiting reduced current leakage and improved reliability is obtained by subjecting an as deposited SiCOH dielectric film to a DUV laser anneal. The DUV laser anneal step of the present invention likely removes the weakly bonded C from the film, thus improving leakage current.

DUV laser annealing and stabilization of SiCOH films

Growing community of inventors

Yorktown Heights, NY, United States of America

Alessandro Cesare Callegari