Stmicroelectronics S.r.l.

Alessandro Camera

Ignazio Salvatore Bellomo

Paolo Sandri

Filippo Marino

Albino Pidutti

Giulio Renato Corva

An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.

Apparatus for verifying the data retention in non-volatile memories

An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.

Integrated device with trimming elements

The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.

Constant-frequency control circuit for a switching voltage regulator of the hysteretic type

A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell. The low threshold voltage level is compared in the memory location currently being addressed as determined in the reading with a stored value corresponding to the lowest of the low threshold voltages of the memory locations previously addressed.

Method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory

An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided. According to the method, the input node is pulled-up to the level of a supply voltage at least when the input node receives a floating voltage, and such pulling-up of the input node is inhibited at least when the input node receives a high voltage signal whose level is higher than the level of the supply voltage.

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Savona, Italy

Alessandro Camera