Micron Technology Incorporated

Alessandro Calderoni

Durai Vishak Nirmal Ramaswamy

Adam D Johnson

Scott E Sills

Ashonita A Chavan

Gurtej S Sandhu

Brent Keeth

Kirk D Prall

Ferdinando Bedeschi

Wayne I Kinney

Beth R Cook

Bei Wang

Paolo Fantini

Massimo Ferro

Lei Bi

Emiliano Faraoni

Haitao Liu

Kamal M Karda

Richard Edward Fackenthal

Karthik Sarpatwari

Duane R Mills

Angelo Visconti

Marcello Mariani

Giorgio Servalli

Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.

Differential storage in memory arrays

Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

Memory device having 2-transistor vertical memory cell and shield structures

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

Methods of forming structures containing leaker-devices and memory configurations incorporating leaker-devices

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

Memory cell imprint avoidance

An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.

Array of cross point memory cells

Methods of incorporating leaker-devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker-devices

Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.

Memory systems and memory programming methods

Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

Cell performance recovery using cycling techniques

Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.

Ferroelectric memory and methods of forming the same

The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

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Boise, ID, United States of America

Alessandro Calderoni