Lsi Corporation

Future Wei Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Huawei Technologies Co., Limited

Aleksey Alexandrovich Letunovskiy

Ivan Leonidovich Mazurenko

Elyar Eldarovich Gasanov

Pavel Anatolyevich Panteleev

Gleb Vyacheslavovich Kalachev

Alexander Alexandrovich Petyushko

Wen Tong

Alexander Markovic

Carmela Cozzo

Pavel Aleksandrovich Aliseychik

Denis Vladimirovich Parkhomenko

Dmitry Nicolaevich Babin

Alexander Borisovich Kholodenko

Denis Vassilevich Parfenov

Andrey Nikitin

Yurii Sergeevich Shutkin

Denis Vladimirovich Zaytsev

Fan Zhang

Anatoli Aleksandrovich Bolotov

Lav D Ivanovic

Jiang Li

Alexei Vladimirovich Galatenko

Ilya Viktorovich Lyalin

Denis Vasilyevich Parfenov

Pavel Aleksandrovich Aliseitchik

Dmitriy Vladimirovich Alekseev

A method for generating a code, a method for encoding and decoding data, and an encoder and a decoder performing the encoding and decoding are disclosed. In an embodiment, a method for lifting a child code from a base code for encoding and decoding data includes determining a single combination of a circulant size, a lifting function, and a labelled base matrix PCM according to an information length and a code rate using data stored in a lifting table. The lifting table was defined at a code generation stage. The method also includes calculating a plurality of shifts for the child code. Each shift is calculated by applying the lifting function to the labelled base matrix PCM with a defined index using the circulant size and using the derived child PCM to encode or decode data.

Multi-label offset lifting method

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.

Method and apparatus for encoding and decoding LDPC codes

A method and system for offset lifting is provided. In an embodiment, a method for encoding data includes receiving a K-bit source word input. The method also includes encoding the K-bit source word input according to a LDPC code, a lifting function, and a circulant size offset to generate an N-bit code word output. The circulant size and lifting function are determined according to an information length, a code rate, and a decoder. The method also includes storing the N-bit code word output in input/output memory.

Method for generating parity check matrix for low density parity check coding

An image processing system comprises an image processor configured to construct a designated functional based on a plurality of functions each associated with a corresponding portion of image information relating to at least first and second images, and to generate a target image utilizing the constructed functional. For example, the functions may comprise a set of functions &#x192;(A), &#x192;(A), . . . , &#x192;(A) of pixels from respective input images A, A, Aof the image information, and the functional may be a function F(X) of the set of functions &#x192;,(A) &#x192;(A), &#x192;(A) where X denotes the target image and is generated by minimizing the functional F(X). The input images may be received from one or more image sources and the target image may be provided to one or more image destinations.

Target image generation utilizing a functional based on functions of information from other images

An image processing system comprises an image processor configured to identify edges in an image, to apply a first type of filtering operation to portions of the image associated with the edges, and to apply a second type of filtering operation to one or more other portions of the image. By way of example only, in a given embodiment a clustering operation is applied to the image to identify a plurality of clusters, a first set of edges comprising edges of the clusters is identified, an edge detection operation is applied to the image to identify a second set of edges, a third set of edges is identified based on the first and second sets of edges, and the first type of filtering operation is applied to portions of the image associated with one or more edges of the third set of edges.

Image processor with edge-preserving noise suppression functionality

An image processor comprises image processing circuitry implementing a plurality of processing layers including at least an evaluation layer and a recognition layer. The evaluation layer comprises a software-implemented portion and a hardware-implemented portion, with the software-implemented portion of the evaluation layer being configured to generate first object data of a first precision level using a software algorithm, and the hardware-implemented portion of the evaluation layer being configured to generate second object data of a second precision level lower than the first precision level using a hardware algorithm. The evaluation layer further comprises a signal combiner configured to combine the first and second object data to generate output object data for delivery to the recognition layer. By way of example only, the evaluation layer may be implemented in the form of an evaluation subsystem of a gesture recognition system of the image processor.

Image processor with evaluation layer implementing software and hardware algorithms of different precision

A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.

Test signal generator for low-density parity-check decoder

An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.

Dynamically controlling the number of local iterations in an iterative decoder

A video transcoder for converting an encoded input video bit-stream having one spatial resolution into an encoded output video bit-stream having a lower spatial resolution, wherein learned statistics of intra-mode transcoding are used to constrain the search of intra modes for the output video bit-stream. The statistics of intra-mode transcoding can be gathered, e.g., by applying brute-force downsizing to a training set of video frames and then analyzing the observed intra-mode transcoding patterns to determine a transition-probability matrix for use during normal operation of the transcoder. The transition-probability matrix enables the transcoder to select appropriate intra modes for the output video bit-stream without performing a corresponding exhaustive full search, which advantageously reduces the computational complexity and processor load compared to those of a comparably performing prior-art video transcoder.

Intra-mode prediction for a video transcoder

In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame.

High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs)

A video transcoder for converting a compressed input video bit-stream having one spatial resolution into a compressed output video bit-stream having a different spatial resolution in a manner that enables the transcoder to dynamically change the amount of computational resources allocated to the conversion process. In one embodiment, the video transcoder has a plurality of configurable processing paths whose configuration determines the amount of allocated computational resources. Exemplary processing-path configuration changes may include, but are not limited to engaging or disengaging a processing path, redirecting a data flow from flowing through one processing path to flowing through another processing path, and attaching or detaching one or more processing modules to an engaged processing path. The capability to make these and other configuration changes enables the video transcoder to adjust the computational complexity and picture quality on the fly, without interrupting the video sequence in the output video bit-stream.

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Moscow, Russia

Aleksey Alexandrovich Letunovskiy