Nvidia Corporation

Phoenix Technologies Ltd.

Aleksandr Frid

Parthasarathy Sriram

Arman Toorians

Anthony Paul Casano

Scott Alan Williams

Chung-Yuan Huang

Ming-Lung Chiu

Satya Kiran Popuri

Ilan Aelion

Chia-Ching Lin

Chien-Ting Yeh

Udaykumar Raval

Shailendra Chafekar

A clock frequency controller for a processor and a method of operation thereof. The clock frequency controller may be embodied in a processor, including: (1) a processing core operable at a clock frequency to undertake a processing of a graphics application, and (2) a clock frequency controller coupled to the processing core and operable to adjust the clock frequency based on a current frame rate of the processing and a target frame rate for the processing.

Processor frequency mainly depending on a target frame rate while processing a graphics application

A method for communication over an SMB, I2C bus, or other serial bus between an auxiliary display subsystem and a secondary processor of a notebook including the auxiliary display subsystem, and systems, circuits and notebooks configured to perform the method. Typically, communication over the serial bus between the auxiliary display subsystem and secondary processor can occur when the notebook is in a standby or other low-power state (e.g., to obtain system status data or cause the notebook to wake up) or a fully-powered normal operating state. Typically, the auxiliary display subsystem is coupled not only to the notebook's secondary processor by the serial bus but also to the notebook's central processing unit by another link (e.g., a USB).

Method and system for communication between a secondary processor and an auxiliary display subsystem of a notebook

A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.

Power management with dynamic frequency adjustments

To reduce power consumption, a processor can be placed into a reduced power state. Before doing so, interrupt events can be designated as wakeup events. While the processor is in the reduced power state, if an event designated as a wakeup event occurs, then a signal is directed to a wakeup event handler instead of to an interrupt handler. In response to the signal, the wakeup event handler causes power to be restored to the processor, so that the event can be subsequently serviced.

Responding to interrupts while in a reduced power state

A method and system for enabling an auxiliary system to retrieve the system information from a computing device are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of requesting for the system information from an embedded controller of the computing device through a first bi-directional data bus if the computing device is shut down, requesting for the system information from the computing device through the first bi-directional bus during the boot-up sequence of the computing device, and requesting for the system information from the computing device through a general purpose input/output (GPIO) after the computing device completes the boot-up sequence.

Method and system for enabling an auxiliary system to retrieve system information from a computing device

A method and apparatus for enabling the use of two or more pointing devices with a computer, where the pointing devices generate data packets of different sizes. The maximum size of the data packets generated by the pointing devices is determined. Any data packets received from the pointing devices which are smaller than the maximum size have additional bytes added to increase the size of the data packet to the maximum size. Thus, the computer receives the same size data packets from all of the pointing devices, facilitating the use of multiple pointing devices.

System and method for synchronization of pointing devices with different

A single controller handles keyboard functions and ACPI configuration and power management functions, while providing priority to keyboard functions so that there is no end user-perceptible compromise of keyboard functionality. When an interrupt is received by the microcontroller, it is determined whether the interrupt is an embedded controller interrupt received at the embedded controller host interface or a keyboard interrupt received at the keyboard host interface. If the interrupt is a keyboard interrupt, the keyboard function is handled in a standard fashion. If the interrupt is an embedded controller interrupt for an ACPI configuration or power management function, a burst timer is started and the command is handled by a command dispatcher. If the embedded controller is in burst mode, multiple commands may be received during a burst period. Commands which are not completed before the expiration of the burst timer are aborted, and a data return vector is set to the absolute address at the point of abortion in the firmware. Aborted commands are resumed on reception of the next embedded controller interrupt by continuation of the process at the data return vector address.

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San Francisco, CA, United States of America

Aleksandr Frid