Intel Corporation

Aleksandar Aleksov

Johanna M Swan

Feras Eid

Adel A Elsherbini

Telesphor Kamgaing

Georgios C Dogiamis

Shawna M Liff

Sasha N Oster

Henning Braunisch

Kristof Darmawikarta

Veronica Aleman Strong

Robert Alan May

Sri Ranga Sai Boyapati

Brandon M Rawlings

Srinivas V Pietambaram

Thomas L Sounart

Sujit Sharan

Krishna Bharath

Mathew J Manusharow

Dilan Seneviratne

Javier Soto Gonzalez

Richard J Dischler

Chia-Pin Chiu

Suddhasattwa Nad

Stefanie M Lotz

Nadine L Dabby

Valluri Ramana Rao

Ravindranath Vithal Mahajan

Hiroki Tanaka

Braxton L Lathrop

Yidnekachew S Mekonnen

Robert L Sankman

Kimin Jun

Jeremy D Ecton

Amit S Baxi

Vincent S Mageshkumar

Brandon C Marin

Rajendra C Dias

Changhua Liu

Neelam Prabhu Gaunkar

Meizi Jiao

Gilbert W Dewey

Brian S Doyle

Mauro J Kobrinsky

Rahul N Manepalli

John Stephen Guzek

Zhichao Zhang

Yonggang Li

Leonel R Arana

Hyung-Jin Lee

Steve S Cho

Xiaoying Guo

Ting Zhong

Han Wui Then

Qing Ma

Zhiguo Qian

William J Lambert

Gerald S Pasdast

Robert Starkston

Edward Rudolph Prack

Mark S Hlad

Patrick R Morrow

Paul B Fischer

Ofir Degani

Omkar G Karhade

Nitin A Deshpande

Sanka Ganesan

Mihir K Roy

Eyal Fayneh

Rajasekaran Swaminathan

Vivek Raghunathan

Rajashree Raji Baskaran

Gang Duan

Andrew James Brown

Brennen Karl Mueller

Prithwish Chatterjee

Kumar Ranganathan

Kevin P O'brien

Ian A Young

Van H Le

Debendra Mallik

Kaan Oguz

Randy B Osborne

Lakshman Krishnamurthy

Kaladhar Radhakrishnan

Kyu Oh Lee

Sairam Agraharam

Joshua Heppner

Rahul Jain

John C Johnson

Sai Vadlamani

Tarek A Ibrahim

Andrew Paul Collins

Pramod Malatkar

Jianyong Xie

Julien Sebot

Manish Dubey

Daniel N Sobieski

Beomseok Choi

Steven A Klein

Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Compact surface transmission line waveguides with vertical ground planes

Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

RF filters and multiplexers manufactured in the core of a package substrate using glass core technology

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Package substrate with glass core having vertical power planes for improved power delivery

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

First layer interconnect first on carrier approach for EMIB patch

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.

Microelectronic assemblies

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

Capacitors and resistors at direct bonding interfaces in microelectronic assemblies

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Thermal management in integrated circuit packages

Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Airgap structures for high speed signal integrity

Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Low leakage thin film capacitors using titanium oxide dielectric with conducting noble metal oxide electrodes

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

Multi-chip package with high density interconnects

Growing community of inventors

Chandler, AZ, United States of America

Aleksandar Aleksov