Intel Corporation

Aleksandar Aleksov

Johanna M Swan

Feras Eid

Adel A Elsherbini

Telesphor Kamgaing

Georgios C Dogiamis

Shawna M Liff

Sasha N Oster

Henning Braunisch

Kristof Darmawikarta

Veronica Aleman Strong

Robert Alan May

Srinivas V Pietambaram

Sri Ranga Sai Boyapati

Brandon M Rawlings

Thomas L Sounart

Sujit Sharan

Krishna Bharath

Mathew J Manusharow

Dilan Seneviratne

Javier Soto Gonzalez

Suddhasattwa Nad

Richard J Dischler

Chia-Pin Chiu

Hiroki Tanaka

Stefanie M Lotz

Valluri Ramana Rao

Ravindranath Vithal Mahajan

Kimin Jun

Jeremy D Ecton

Braxton L Lathrop

Yidnekachew S Mekonnen

Robert L Sankman

Brandon C Marin

Amit S Baxi

Vincent S Mageshkumar

Changhua Liu

Neelam Prabhu Gaunkar

Leonel R Arana

Rajendra C Dias

Steve S Cho

Xiaoying Guo

Meizi Jiao

Gilbert W Dewey

Brian S Doyle

Mauro J Kobrinsky

Rahul N Manepalli

John Stephen Guzek

Zhichao Zhang

Yonggang Li

Hyung-Jin Lee

Han Wui Then

Stephen L Morein

Qing Ma

Zhiguo Qian

William J Lambert

Gerald S Pasdast

Gang Duan

Robert Starkston

Edward Rudolph Prack

Prithwish Chatterjee

Mark S Hlad

Patrick R Morrow

Paul B Fischer

Omkar G Karhade

Ofir Degani

Nitin A Deshpande

Sanka Ganesan

Mihir K Roy

Eyal Fayneh

Yoshihiro Tomita

Rajasekaran Swaminathan

Vivek Raghunathan

Rajashree Raji Baskaran

Andrew James Brown

Julien Sebot

Brennen Karl Mueller

Kevin P O'brien

Ian A Young

Van H Le

Debendra Mallik

Kaan Oguz

Randy B Osborne

Lakshman Krishnamurthy

Kaladhar Radhakrishnan

Kyu Oh Lee

Sairam Agraharam

Rahul Jain

Joshua Heppner

Sai Vadlamani

John C Johnson

Andrew Paul Collins

Tarek A Ibrahim

Pramod Malatkar

Jianyong Xie

Xavier Francois Brun

Manish Dubey

Daniel N Sobieski

Beomseok Choi

Steven A Klein

Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Substrate integrated thin film capacitors using amorphous high-k dielectrics

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

Cooling of conformal power delivery structures

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

First layer interconnect first on carrier approach for EMIB patch

Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

Hybrid bonding technologies with thermal expansion compensation structures

Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

Physical vapor deposition seeding for high aspect ratio vias in glass core technology

Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries

Technologies for high throughput additive manufacturing for integrated circuit components

Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

Compact surface transmission line waveguides with vertical ground planes

Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

RF filters and multiplexers manufactured in the core of a package substrate using glass core technology

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

Package substrate with glass core having vertical power planes for improved power delivery

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

Growing community of inventors

Chandler, AZ, United States of America

Aleksandar Aleksov