Intel Corporation

Alekhya Nimmagadda

Travis W LaJoie

Van H Le

Abhishek A Sharma

Bernhard Sell

Hui Jae Yoo

Wilfred Gomes

Fatih Hamzaoglu

Miriam Ruth Reshotko

Pei-Hua Wang

Juan G Alzate-Vinasco

Albert Chen

Chieh-jen Ku

Described herein are integrated circuit devices with semiconductor devices and interconnects coupled to contacts of the semiconductor devices, where the interconnects have tungsten liners between a fill material of the interconnect and the contacts. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. Tungsten liners may be in combination with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

Integrated circuits with tungsten interconnect liners

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

Backend memory with air gaps in upper metal layers

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Hillsboro, OR, United States of America

Alekhya Nimmagadda