Intel Corporation

Alejandro Vicente Martinez

Fernando Latorre

Pedro Lopez

Raul Martinez

Josep M Codina

Enric Gibert Codina

Carlos Madriles

Antonio Gonzalez

Grigorios Magklis

Marc Lupon

Pedro Marcuello

Polychronis Xekalakis

Daniel Ortega

Kyriakos A Stavrou

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Crispin Gomez Requena

Christos E Kotselidis

Antonio Gonzelez

A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Instruction and logic for optimization level aware branch prediction

Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.

Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

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Barcelona, Spain

Alejandro Vicente Martinez