Intel Corporation

Alejandro Martinez Vicente

Antonio Gonzalez

Fernando Latorre

Grigorios Magklis

Pedro Lopez

Marc Lupon

Pedro Marcuello

Polychronis Xekalakis

Josep M Codina

Raul Martinez

Enric Gibert Codina

Kyriakos A Stavrou

Daniel Ortega

Demos Pavlou

Georgios Tournavitis

Mirem Hyuseinova

Crispin Gomez Requena

Christos E Kotselidis

Carlos Madriles

Carlos Madriles Gimeno

Marti Torrents Lapuerta

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

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Barcelona, Spain

Alejandro Martinez Vicente