Intel Corporation

Alec W Smidt

Sean Stephen Eilert

Kerry Dean Tedrow

Gerald J Barkley

Matthew Goldman

Reed Linde

Ravi Annavajjhala

Andrew D Proescholdt

Boubekeur Benhamida

In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterable memories may be dynamically mapped.

Dynamically mapping block-alterable memories

According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).

Memory defect detection and self-repair technique

An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.

Apparatuses and methods for pre-charging intermediate nodes for high-speed wordline

A high-speed voltage level shifter. A transistor () may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (), and a driver () connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (). A plurality of series-connected transistors (A&#x2013;N) may be connected between a second node (A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (). A transistor () may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at nodeA, so transistorsA&#x2013;N may be low-voltage, high speed transistors.

Growing community of inventors

Folsom, CA, United States of America

Alec W Smidt