Texas Instruments Corporation

Alec James Morton

Taylor R Efland

Karl H Renner

Chin-Yu Tsai

Michael C Smayling

Ross Eliot Teggatz

Amitava Chatterjee

Satwinder S Malhi

Jozef C Mitros

Joseph A Devore

Mark Stephen Rodder

Seetharaman Sridhar

Byron Lovell Williams

Keith Edmund Kunz

Hisashi Shichijo

James R Hellums

Dan M Mosher

C Matthew Thompson

Erika Leigh Shoemaker

Betty S Mercer

Laurinda W Ng

Ganesh Kamath

Preetham Kumar

Sam Shichijo

Jozef Czeslaw Mitros

The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (), among other elements, includes a surface conductive lead () located in an opening formed within a protective overcoat (), and a barrier layer () located between the protective overcoat () and the surface conductive lead (), a portion of the barrier layer () forming a skirt () that extends outside a footprint of the surface conductive lead ().

Method for manufacturing an interconnect

An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

Embedded EEPROM array techniques for higher density

High performance digital transistors ( ) and analog transistors ( ) are formed at the same time. The digital transistors ( ) include first pocket regions ( ) for optimum performance. These pocket regions ( ) are masked from at least the drain side of the analog transistors ( ) to provide a flat channel doping profile on the drain side. Second pocket regions ( ) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.

Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).

Measuring integrated circuit layout efficiency

An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate ( ) is formed over a CMOS n-well region ( ) and a CMOS p-well region ( ) in a silicon substrate ( ). Transistor source regions ( ), ( ) and drain regions ( ), ( ) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions ( ), ( ) serve as the drain extension regions of the transistor.

Higher voltage transistors for sub micron CMOS processes

High performance digital transistors ( ) and analog transistors ( ) are formed at the same time. The digital transistors ( ) include pocket regions ( ) for optimum performance. These pocket regions ( ) are partially or completely suppressed from at least the drain side of the analog transistors ( ) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors ( ).

METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS

A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits,form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Integrated bipolar junction transistor for mixed signal circuits

The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

Method for current ballasting and busing over active device area using a

Device having current ballasting and busing over active area using a

A digital filter for synthesized speech includes a full adder (72) that is multiplexed to perform multiplication and addition/subtraction operations. The inputs of the adder (72) are multiplexed by multiplexers (90) and (92). The adder (72) calculates Y-values and B-values. The B-values are input to a delay stack (116) and the Y-values are stored in a Y-register (78). One product is generated of a multiplier stored in a K-stack (128) and a multiplicand selected by a multiplexer (122). The multiplicand is a prestored summation that was earlier stored in a sum register (82). This product is stored in an ACC register (74) and utilized in both the calculation of the B-values and the Y-values. Therefore, only one multiplication is required for corresponding Y- and B-values, thereby reducing the number of multiplication steps required in processing each stage of a digital filter.

Linear predictive coding technique with one multiplication step per stage

A lattice filter for processing lattice equations includes a fast adder (78) for adding partial products to partially perform a multiplication step. A full adder (44) is provided for completing the multiplication and then adding the product with a previously calculated and stored value. The input to the full adder (44) is multiplexed with a multiplexer (74) for selecting the sum output of the fast adder (78) and a multiplexer (76) for selecting the carry output of the fast adder (78). The multiplexer (74) also selects prestored values for addition with the summed output of the full adder (44). This summed output is selected by the multiplexer (76). The fast adder (78) sums partial products simultaneous with addition operations of the full adder (44). In this manner, the full adder (44) operates at a slower rate than the fast adder (78). Storage registers (58), (62), (70) are utilized to delay results output by the full adder (44) for later selection and operation thereon. These values are utilized as both the multiplicand the addend in subsequent operations. The multiplier is stored in a K-stack (90) and selected for the appropriate operations. A bit correction circuit (190) provides corrections for truncated bits in the form of a carry input to the full adder (44).

Digital lattice filter with multiplexed fast adder/full adder for

A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit. The addition operation is performed on the generated product by circulating the product back to the B-input of the adder (44) through the multiplexer (66). Data is selected from the output of a data stack (52) or from a D-register (108) which contains a prestored output value.

Digital lattice filter with multiplexed full adder

An LPC digital lattice filter includes a full adder (44) which has one input thereof multiplexed with a multiplexer (46) and the other input thereof multiplexed by a multiplexer (50). Combination of the multiplication and addition steps with the full adder (44) results in the calculation of one of the digital filter equations. The result of each of these equations is either a Y-value or a B-value. The Y-values are stored in the output of a Y-register (78) and the B-values are stored in a nine stage B-stack (100) for delay thereof. The multiplexer (60) selects multiplicands from either the output of the one stage delay (86), from the B-stack (100) or the input excitation I. The multiplexer (46) selects addends from either the output of the B-stack (100), the output of the B-register (96) or from the multiplexers (60) or (66). The values are calculated in an interleaved sequence with a Y-value calculated and then a B-value calculated utilizing this generated Y-value. This generated Y-value is then used in calculating the next sequential Y-value and then discarded. However, the B-values are delayed until calculation of the next set of equations. The interleaved sequence allows use of only one set of delay stages.

Linear predictive coding technique with interleaved sequence digital

A digital lattice filter includes a Y-adder (44) and a B-adder (106). The Y-adder (44) calculates the Y-values for a linear predictive coding voice compression technique and the B-adder (106) calculates the B-values. Each of the calculated B-values output by the B-adder (106) is input to a B-stack (118) for storage therein. The B-stack (118) delays the B-values for one sample period. Multiplier constants are contained in a K-stack (90) for output to both adders (44) and (106) for use in the multiplication operation. The final value is stored in a Y1-register (104). Each of the adders (44) and (106) are multiplexed to perform a multiplication operation followed by an addition operation to generate the respective Y- and B-values. A generated Y-value is stored in a Y-register (56) for use in the next sequential Y calculation. In addition, the generated Y-value is used as a multiplicand for generation of a B-value. Therefore, it is only necessary to store the Y-values for one clock cycle and the B-values for up to nine clock cycles, thus reducing the amount of storage space necessary. In addition, the use of two multiplexed adders reduces the required processing speed at each of the adders.

Growing community of inventors

Plano, TX, United States of America

Alec James Morton