Xilinx, Inc.

Alec J Wong

Pradip Jha

Bin Ochotta

Dennis McCrohan

Qin Qiong Zhang

David A Knol

Amit Kasat

Sudipto Chakraborty

Sahil Goyal

Herve Alexanian

Rajvinder S Klair

Brian Cotter

Premduth Vidyanandan

Sheng Zhou

Steven Banks

Nghia Do

Satyam Jani

Approaches for protection of HLL simulation models in a circuit design having unprotected high-level language (HLL) program code and first metadata of a shared library of executable simulation models that are based on sensitive HLL simulation models. A design tool determines a first storage location of the shared library based on the first metadata and compiles the unprotected HLL program code into an executable object. The design tool links the executable object with the library of executable simulation models from the first storage location and then simulates the circuit design by executing the executable object and loading the executable simulation models in response to initiation by the executable object.

Protection of high-level language simulation models

Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected design is decrypted into a plain design using the session key.

Protection of electronic designs

High level synthesis for a circuit design may include detecting, using a processor, an encrypted, high level programming language (HLL) core for inclusion in a circuit design, decrypting, using the processor, the encrypted HLL core into volatile memory, and generating, using the processor, an encrypted, intermediate representation (IR) of the circuit design including an encrypted IR of the HLL core. An encrypted hardware description language (HDL) circuit design may be generated, using the processor, from the encrypted IR of the circuit design. The encrypted HDL circuit design includes an encrypted HDL core that is functionally equivalent to the encrypted HLL core.

High level programming language core protection for high level synthesis

Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.

Message filtering for electronic design automation systems

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San Jose, CA, United States of America

Alec J Wong